diff options
| -rw-r--r-- | src/cpu/intel/model_6ex/model_6ex_init.c | 94 | ||||
| -rw-r--r-- | src/cpu/intel/model_6fx/microcode_m206f257.h | 291 | ||||
| -rw-r--r-- | src/cpu/intel/model_6fx/microcode_m206f6c7.h | 291 | ||||
| -rw-r--r-- | src/cpu/intel/model_6fx/model_6fx_init.c | 146 |
4 files changed, 817 insertions, 5 deletions
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 169b908901..6ecaca6d15 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -52,6 +52,76 @@ static void fill_processor_name(char *processor_name) strcpy(processor_name, processor_name_start); } +#define IA32_FEATURE_CONTROL 0x003a + +#define CPUID_VMX (1 << 5) +#define CPUID_SMX (1 << 6) +static void enable_vmx(void) +{ + struct cpuid_result regs; + msr_t msr; + + msr = rdmsr(IA32_FEATURE_CONTROL); + + if (msr.lo & (1 << 0)) { + /* VMX locked. If we set it again we get an illegal + * instruction + */ + return; + } + + regs = cpuid(1); + if (regs.ecx & CPUID_VMX) { + msr.lo |= (1 << 2); + if (regs.ecx & CPUID_SMX) + msr.lo |= (1 << 1); + } + + wrmsr(IA32_FEATURE_CONTROL, msr); + + msr.lo |= (1 << 0); /* Set lock bit */ + + wrmsr(IA32_FEATURE_CONTROL, msr); +} + +#define PMG_CST_CONFIG_CONTROL 0xe2 +static void configure_c_states(void) +{ + msr_t msr; + + msr = rdmsr(PMG_CST_CONFIG_CONTROL); + msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk + + // TODO Do we want Deep C4 and Dynamic L2 shrinking? + wrmsr(PMG_CST_CONFIG_CONTROL, msr); +} + +#define IA32_MISC_ENABLE 0x1a0 +static void configure_misc(void) +{ + msr_t msr; + + msr = rdmsr(IA32_MISC_ENABLE); + msr.lo |= (1 << 3); /* TM1 enable */ + msr.lo |= (1 << 13); /* TM2 enable */ + msr.lo |= (1 << 17); /* Bidirectional PROCHOT# */ + + msr.lo |= (1 << 10); /* FERR# multiplexing */ + + // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 + msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + + // TODO Do we want Deep C4 and Dynamic L2 shrinking? + wrmsr(IA32_MISC_ENABLE, msr); + + msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ + wrmsr(IA32_MISC_ENABLE, msr); +} + +#if CONFIG_USBDEBUG_DIRECT +static unsigned ehci_debug_addr; +#endif + static void model_6ex_init(device_t cpu) { char processor_name[49]; @@ -66,13 +136,35 @@ static void model_6ex_init(device_t cpu) fill_processor_name(processor_name); printk_info("CPU: %s.\n", processor_name); +#if CONFIG_USBDEBUG_DIRECT + // Is this caution really needed? + if(!ehci_debug_addr) + ehci_debug_addr = get_ehci_debug(); + set_ehci_debug(0); +#endif + /* Setup MTRRs */ x86_setup_mtrrs(36); x86_mtrr_check(); - + +#if CONFIG_USBDEBUG_DIRECT + set_ehci_debug(ehci_debug_addr); +#endif + /* Enable the local cpu apics */ setup_lapic(); + /* Enable virtualization */ + enable_vmx(); + + /* Configure C States */ + configure_c_states(); + + /* Configure Enhanced SpeedStep and Thermal Sensors */ + configure_misc(); + + /* TODO: PIC thermal sensor control */ + /* Start up my cpu siblings */ intel_sibling_init(cpu); } diff --git a/src/cpu/intel/model_6fx/microcode_m206f257.h b/src/cpu/intel/model_6fx/microcode_m206f257.h new file mode 100644 index 0000000000..96977667b5 --- /dev/null +++ b/src/cpu/intel/model_6fx/microcode_m206f257.h @@ -0,0 +1,291 @@ +//+++ +// Copyright (c) <1995-2008>, Intel Corporation. +// All rights reserved. +// +// Redistribution. Redistribution and use in binary form, without modification, are +// permitted provided that the following conditions are met: +// .Redistributions must reproduce the above copyright notice and the following +// disclaimer in the documentation and/or other materials provided with the +// distribution. +// .Neither the name of Intel Corporation nor the names of its suppliers may be used +// to endorse or promote products derived from this software without specific prior +// written permission. +// .No reverse engineering, decompilation, or disassembly of this software is +// permitted. +// ."Binary form" includes any format commonly used for electronic conveyance +// which is a reversible, bit-exact translation of binary representation to ASCII or +// ISO text, for example, "uuencode." +// +// DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +// HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER +// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +// NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//--- +/* Wed Sep 10 11:53:28 CST 2008 */ +/* 2129-m206f257.inc */ +0x00000001, 0x00000057, 0x03152007, 0x000006f2, +0x07e77759, 0x00000001, 0x00000020, 0x00000fd0, +0x00001000, 0x00000000, 0x00000000, 0x00000000, +0xf0aefac0, 0x7c38e188, 0xba5a013f, 0xdfb167bf, +0x3c3fed5c, 0x9a7527d0, 0x7f3ae5a3, 0x8ab688d1, +0x348436ab, 0xdc4756d5, 0xfc2a0a22, 0x9f11b7bf, +0xa47e1335, 0xc1e04f7c, 0xdaaf86cf, 0xa870c161, +0x072e2279, 0x87ee60b8, 0x3e4b0622, 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0xc936f475, 0x7270925a, 0x30024230, +0x8e72f53d, 0x2b6c1b6f, 0x1a69732c, 0x7ed5aff5, +0xfc18a2a3, 0xaf377cc1, 0xbff09a78, 0x4b4e0814, +0x95a0b2c1, 0x270398de, 0x201fca94, 0x2a032a4f, +0x131542b4, 0x0d7306da, 0x2d1c3496, 0xcc3c6d8d, +0xa814ddc9, 0xa3b3a991, 0x17ee60c2, 0x852c0b8d, +0x11e5853a, 0x762002a7, 0x92c5311d, 0x0d4bf7e1, +0xfffec870, 0xe3d35e5b, 0xff6ecfb9, 0xdedae6ff, +0x0111a772, 0x9808e780, 0x29c336e8, 0xe9bc05df, +0x5bedde11, 0x945565af, 0xaff808fe, 0x87e3423d, +0x4de6f98f, 0x93b4adef, 0xbf704fa4, 0x09120e91, +0xd54f3692, 0xdf8eab1e, 0xfabbf59c, 0xe74318be, +0xaab87ffc, 0x29fa791c, 0xe3915552, 0xa652cb9b, +0xa1252e74, 0xb35b723b, 0x542aa28b, 0x12fcc5b0, +0x3941f962, 0x82bcc6cc, 0x47b11974, 0xb821611f, +0x78b34250, 0xf1be5659, 0x561b9e61, 0x6f3bd501, +0x584e6f5c, 0xd54ed547, 0xacebcd21, 0x7b5ff816, +0xb64ad233, 0x9f2f330d, 0x69fb1ece, 0xac8710dd, +0x58dc6c60, 0x9bee6139, 0xbb10ad0e, 0xbd8cd5dd, +0xebc0ce9d, 0xa733274f, 0x884d9b55, 0x42b08b63, +0xafa54a74, 0x1c7ccf64, 0x93a20191, 0xaaa3132e, +0xc69831d1, 0x54634889, 0xfbfe3efc, 0xd3cf68d4, +0x302e3117, 0xf5693131, 0xc3ce8c6c, 0x1f03cd89, +0x6243334c, 0xf16bc80f, 0xdca5f130, 0xcb2cd956, +0x4c1bb421, 0xe8de533c, 0x7f86703a, 0x29aa897e, +0xdd54acad, 0x76b2f2ae, 0x7ef82b71, 0x2e30970b, +0xba402597, 0x9a653ab4, 0xd68fcf53, 0x2d9f0d15, +0x7f9efd1c, 0x2363d147, 0x5327289a, 0xe89229f3, +0xd63a535c, 0x7efe9273, 0x64f2e3a3, 0x9bdf65a7, +0x26b6edfb, 0x1b9c7bfe, 0x5d14b3de, 0x54d575fb, +0x6d65db4c, 0x95648b7f, 0xa8a3b8f0, 0x7cc7ad46, +0xe20e6dbb, 0x8488a45f, 0x8ebc2932, 0xd4767316, +0x3e8c4b8a, 0xbab7402c, 0xfc1e217e, 0xe5c5bf82, +0x6928fe2e, 0xc88528e9, 0x4b2e4e8f, 0xdd938b86, +0x0c964f98, 0xfc88d480, 0x35fcaf9e, 0xdd7bbe9d, +0x197d005a, 0x4d40b3b3, 0xcf203155, 0x0d2fa621, +0x752d2c58, 0xb12bac12, 0x1e7e8c23, 0x94215d54, +0x9854a71c, 0x4de63c64, 0x7a012529, 0x9c171f8d, +0x9e71def7, 0x3bd17d50, 0x11f175d9, 0xec78abf3, +0x7b529eee, 0xd3a69fc3, 0x5b718676, 0x58214d29, +0xa8bd2c34, 0x41ea00ab, 0xa03f64d6, 0x4ee342b0, +0x32b1e444, 0x1c1801a4, 0xc8424702, 0x334a7e35, +0x50cf1543, 0x3b22b495, 0x88683776, 0x8e2e0154, +0x6155c033, 0x4e2fa6ac, 0x42ace700, 0x8d64f97c, +0xaf9ced17, 0xb2a5cb92, 0xa558582d, 0x88705de7, +0x9e528d59, 0x84bd45e4, 0x5cb680c0, 0xcd48fa5c, diff --git a/src/cpu/intel/model_6fx/microcode_m206f6c7.h b/src/cpu/intel/model_6fx/microcode_m206f6c7.h new file mode 100644 index 0000000000..12e58b2166 --- /dev/null +++ b/src/cpu/intel/model_6fx/microcode_m206f6c7.h @@ -0,0 +1,291 @@ +//+++ +// Copyright (c) <1995-2008>, Intel Corporation. +// All rights reserved. +// +// Redistribution. Redistribution and use in binary form, without modification, are +// permitted provided that the following conditions are met: +// .Redistributions must reproduce the above copyright notice and the following +// disclaimer in the documentation and/or other materials provided with the +// distribution. +// .Neither the name of Intel Corporation nor the names of its suppliers may be used +// to endorse or promote products derived from this software without specific prior +// written permission. +// .No reverse engineering, decompilation, or disassembly of this software is +// permitted. +// ."Binary form" includes any format commonly used for electronic conveyance +// which is a reversible, bit-exact translation of binary representation to ASCII or +// ISO text, for example, "uuencode." +// +// DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +// HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER +// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +// NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//--- +/* Wed Sep 10 11:53:28 CST 2008 */ +/* 2127-m206f6c7.inc */ +0x00000001, 0x000000c7, 0x03152007, 0x000006f6, +0xd863aca5, 0x00000001, 0x00000020, 0x00000fd0, +0x00001000, 0x00000000, 0x00000000, 0x00000000, +0xf135893c, 0x4c42e3f3, 0xb73a55b6, 0x351ee5de, +0xb62b15d8, 0xa4b7a683, 0x15e59363, 0xb5a88344, +0x83cb3484, 0x27b18c8d, 0x94d04ac1, 0x8f1f77db, +0x13b4b7fe, 0xa649fe2c, 0xb24e07e8, 0x1599f3a0, +0xb3769963, 0xa12ac372, 0x250722b3, 0x9d15fb7d, +0x9813a1b2, 0x117335fd, 0x8c1230f9, 0x81968e27, +0x05a86156, 0x9b82a393, 0x9169c94d, 0x31b89d77, +0x973c1fb2, 0x8f75d325, 0x6386e9f8, 0xa8df1a90, +0xea70b02b, 0x5eb51ed7, 0x8c97f33c, 0xf9c1b8a6, +0x5eb80126, 0xbec523d7, 0xb974f767, 0x73b44b82, +0xf832f648, 0x8d196107, 0x7c0879bf, 0xcd6d630c, +0x22466897, 0x4816ea2d, 0x6efda835, 0x25832e9b, +0x7898d668, 0x59131743, 0x0f5c9772, 0x6f5a9ec7, +0xbe40da64, 0x2d376de9, 0x85fdddd4, 0x9721c351, +0x12a9d1de, 0xbfb37d7c, 0xb21a779f, 0x2593f254, +0xa1737d77, 0x9aa94919, 0x314de914, 0xb56a3111, +0x82a98637, 0x15fcc11e, 0x882e1550, 0x9dc71080, +0x2effb94c, 0xaca5f479, 0xaa2db04b, 0x2ec75a37, +0x80c324c1, 0xb387798a, 0x092e24c6, 0x82f54f78, +0x2799d295, 0x010b6198, 0x38d497ab, 0x255044a9, +0x28f09f9f, 0x12e3669b, 0x2937f975, 0x21332882, +0x2a0c3de4, 0x127b6e06, 0x196c4c4a, 0x339de5f3, +0x2d1952eb, 0x11b661e9, 0x38c5a4d9, 0x08d02b39, +0x07714640, 0x14394d59, 0x3e2f5bbd, 0x0898e888, +0x3ebde0c8, 0x11078f3c, 0x32e047cd, 0x3b8a1671, +0x3d5400a2, 0x1ee97d92, 0x057760c9, 0x31ddc483, +0x6b672bb1, 0x0239c65b, 0x5168de3c, 0x57da3987, +0x0a411c03, 0x6ac8c9c3, 0x38c1814d, 0x138ae982, +0x17fe9610, 0x22c1b2c2, 0x0f64d62b, 0x292f29a6, +0x172bd3a3, 0x2660983f, 0x3f34706f, 0x17ddc325, +0x3be7c056, 0x24297b2c, 0x0d7b4a97, 0x1ccace5e, +0x362c300c, 0x2d8a24c7, 0x40a8b209, 0x27e2b212, +0x51f58204, 0x47291d65, 0x049de5d0, 0x620f697e, +0x4a407809, 0x2c8afcc9, 0x3adb22f4, 0x4dec3b92, +0x46981a3b, 0x379b774c, 0x7f3ab853, 0x7d8d941d, +0x35d5717b, 0x4865f240, 0x657ae90a, 0x38db767f, +0x5ba5af85, 0x624bde90, 0x27ca5b94, 0x7d6de192, +0x74752869, 0x1aa685e2, 0x626ac31b, 0x78db6d6c, +0x10924be8, 0x7f5fa69a, 0x70b7ba13, 0x35ea4627, +0x6e8d8ce0, 0x5a36f924, 0x368ab401, 0x7271a3bb, +0x5a552eaa, 0x32d42181, 0x6db87723, 0x6459b69e, +0x3b7f2229, 0x516935fe, 0x7af35a05, 0x34d6f025, +0x4fb65637, 0x7f9446c9, 0x29279aae, 0x630458d9, +0x7d91017f, 0x12138189, 0x670175f5, 0x79410f28, +0x10096979, 0x6c00509a, 0x65007291, 0x231b6f99, +0x6c086043, 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0x4ee342b0, +0x32b1e444, 0x1c1801a4, 0xc8424702, 0x334a7e35, +0x50cf1543, 0x3b22b495, 0x88683776, 0x8e2e0154, +0x6155c033, 0x4e2fa6ac, 0x42ace700, 0x8d64f97c, +0xaf9ced17, 0xb2a5cb92, 0xa558582d, 0x88705de7, +0x9e528d59, 0x84bd45e4, 0x5cb680c0, 0xcd48fa5c, diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 2ee950bfa0..64f77410aa 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -12,7 +12,8 @@ #include <cpu/x86/mtrr.h> static const uint32_t microcode_updates[] = { - // #include "microcode_m206e839.h" + #include "microcode_m206f257.h" + #include "microcode_m206f6c7.h" /* Dummy terminator */ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, @@ -52,7 +53,121 @@ static void fill_processor_name(char *processor_name) strcpy(processor_name, processor_name_start); } -static void model_6ex_init(device_t cpu) +#define IA32_FEATURE_CONTROL 0x003a + +#define CPUID_VMX (1 << 5) +#define CPUID_SMX (1 << 6) +static void enable_vmx(void) +{ + struct cpuid_result regs; + msr_t msr; + + msr = rdmsr(IA32_FEATURE_CONTROL); + + if (msr.lo & (1 << 0)) { + /* VMX locked. If we set it again we get an illegal + * instruction + */ + return; + } + + regs = cpuid(1); + if (regs.ecx & CPUID_VMX) { + msr.lo |= (1 << 2); + if (regs.ecx & CPUID_SMX) + msr.lo |= (1 << 1); + } + + wrmsr(IA32_FEATURE_CONTROL, msr); + + msr.lo |= (1 << 0); /* Set lock bit */ + + wrmsr(IA32_FEATURE_CONTROL, msr); +} + +#define PMG_CST_CONFIG_CONTROL 0xe2 +#define PMG_IO_BASE_ADDR 0xe3 +#define PMG_IO_CAPTURE_ADDR 0xe4 + +#define PMB0_BASE 0x580 +#define PMB1_BASE 0x800 +#define CST_RANGE 2 +static void configure_c_states(void) +{ + msr_t msr; + + msr = rdmsr(PMG_CST_CONFIG_CONTROL); + + msr.lo |= (1 << 15); // config lock until next reset + msr.lo |= (1 << 14); // Deeper Sleep + msr.lo |= (1 << 10); // Enable IO MWAIT redirection + msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk + msr.lo |= (1 << 3); // Dynamic L2 + + wrmsr(PMG_CST_CONFIG_CONTROL, msr); + + /* Set Processor MWAIT IO BASE */ + msr.hi = 0; + msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16); + wrmsr(PMG_IO_BASE_ADDR, msr); + + /* Set IO Capture Address */ + msr.hi = 0; + msr.lo = ((PMB0_BASE + 4) & 0xffff) | (( CST_RANGE & 0xffff) << 16); + wrmsr(PMG_IO_CAPTURE_ADDR, msr); +} + +#define IA32_MISC_ENABLE 0x1a0 +static void configure_misc(void) +{ + msr_t msr; + + msr = rdmsr(IA32_MISC_ENABLE); + msr.lo |= (1 << 3); /* TM1 enable */ + msr.lo |= (1 << 13); /* TM2 enable */ + msr.lo |= (1 << 17); /* Bidirectional PROCHOT# */ + + msr.lo |= (1 << 10); /* FERR# multiplexing */ + + // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 + msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + + /* Enable C2E */ + msr.lo |= (1 << 26); + + /* Enable C4E */ + /* TODO This should only be done on mobile CPUs, see cpuid 5 */ + msr.hi |= (1 << (32 - 32)); // C4E + msr.hi |= (1 << (33 - 32)); // Hard C4E + + /* Enable EMTTM. */ + /* NOTE: We leave the EMTTM_CR_TABLE0-5 at their default values */ + msr.hi |= (1 << (36 - 32)); + + wrmsr(IA32_MISC_ENABLE, msr); + + msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ + wrmsr(IA32_MISC_ENABLE, msr); +} + +#define PIC_SENS_CFG 0x1aa +static void configure_pic_thermal_sensors(void) +{ + msr_t msr; + + msr = rdmsr(PIC_SENS_CFG); + + msr.lo |= (1 << 21); // inter-core lock TM1 + msr.lo |= (1 << 4); // Enable bypass filter + + wrmsr(PIC_SENS_CFG, msr); +} + +#if CONFIG_USBDEBUG_DIRECT +static unsigned ehci_debug_addr; +#endif + +static void model_6fx_init(device_t cpu) { char processor_name[49]; @@ -66,19 +181,42 @@ static void model_6ex_init(device_t cpu) fill_processor_name(processor_name); printk_info("CPU: %s.\n", processor_name); +#if CONFIG_USBDEBUG_DIRECT + // Is this caution really needed? + if(!ehci_debug_addr) + ehci_debug_addr = get_ehci_debug(); + set_ehci_debug(0); +#endif + /* Setup MTRRs */ x86_setup_mtrrs(36); x86_mtrr_check(); - + +#if CONFIG_USBDEBUG_DIRECT + set_ehci_debug(ehci_debug_addr); +#endif + /* Enable the local cpu apics */ setup_lapic(); + /* Enable virtualization */ + enable_vmx(); + + /* Configure C States */ + configure_c_states(); + + /* Configure Enhanced SpeedStep and Thermal Sensors */ + configure_misc(); + + /* PIC thermal sensor control */ + configure_pic_thermal_sensors(); + /* Start up my cpu siblings */ intel_sibling_init(cpu); } static struct device_operations cpu_dev_ops = { - .init = model_6ex_init, + .init = model_6fx_init, }; static struct cpu_device_id cpu_table[] = { |