diff options
28 files changed, 338 insertions, 258 deletions
diff --git a/src/cpu/amd/socket_940/Config.lb b/src/cpu/amd/socket_940/Config.lb index 4b23f0b46a..cff1c6eab9 100644 --- a/src/cpu/amd/socket_940/Config.lb +++ b/src/cpu/amd/socket_940/Config.lb @@ -1,3 +1,9 @@ -#config chip.h -#object socket_940.o +uses CONFIG_CHIP_NAME + +if CONFIG_CHIP_NAME + config chip.h +end + +object socket_940.o + dir /cpu/amd/model_fxx diff --git a/src/cpu/amd/socket_940/socket_940.c b/src/cpu/amd/socket_940/socket_940.c index 1a781d61e5..d412538ed1 100644 --- a/src/cpu/amd/socket_940/socket_940.c +++ b/src/cpu/amd/socket_940/socket_940.c @@ -1,7 +1,8 @@ #include <device/device.h> #include "chip.h" - +#if CONFIG_CHIP_NAME == 1 struct chip_operations cpu_amd_socket_940_ops = { CHIP_NAME("socket 940") }; +#endif diff --git a/src/mainboard/tyan/s2735/Config.lb b/src/mainboard/tyan/s2735/Config.lb index 52c1ccde4f..3e602fb0d8 100644 --- a/src/mainboard/tyan/s2735/Config.lb +++ b/src/mainboard/tyan/s2735/Config.lb @@ -122,73 +122,77 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc ## Include the secondary Configuration files ## dir /pc80 -config chip.h + +if CONFIG_CHIP_NAME + config chip.h +end # sample config for tyan/s2735 -chip northbridge/intel/e7501 +chip northbridge/intel/e7501/root_complex device pci_domain 0 on - device pci 0.0 on end - device pci 0.1 on end - device pci 2.0 on - chip southbridge/intel/i82870 - device pci 1c.0 on end - device pci 1d.0 on end - device pci 1e.0 on end - device pci 1f.0 on end - end - end - device pci 6.0 on end - chip southbridge/intel/i82801er - device pci 1d.0 on end - device pci 1d.1 on end - device pci 1d.2 on end - device pci 1d.3 on end - device pci 1d.7 on end - device pci 1e.0 on end - device pci 1f.0 on + chip northbridge/intel/e7501 + device pci 0.0 on end + device pci 0.1 on end + device pci 2.0 on + chip southbridge/intel/i82870 + device pci 1c.0 on end + device pci 1d.0 on end + device pci 1e.0 on end + device pci 1f.0 on end + end + end + device pci 6.0 on end + chip southbridge/intel/i82801er + device pci 1d.0 on end + device pci 1d.1 on end + device pci 1d.2 on end + device pci 1d.3 on end + device pci 1d.7 on end + device pci 1e.0 on end + device pci 1f.0 on # device pci 8.0 end - chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # GAME_MIDI_GIPO1 - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - end - end - end - device pci 1f.1 off end - device pci 1f.2 on end - device pci 1f.3 on end - device pci 1f.5 off end - device pci 1f.6 off end - - end - end + chip superio/winbond/w83627hf + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GAME_MIDI_GIPO1 + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + end + end + end + device pci 1f.1 off end + device pci 1f.2 on end + device pci 1f.3 on end + device pci 1f.5 off end + device pci 1f.6 off end + end # SB + end #NB + end # PCI_DOMAIN device apic_cluster 0 on chip cpu/intel/socket_mPGA604_533Mhz device apic 0 on end diff --git a/src/mainboard/tyan/s2735/Options.lb b/src/mainboard/tyan/s2735/Options.lb index 617dfa8650..98c7e50f4f 100644 --- a/src/mainboard/tyan/s2735/Options.lb +++ b/src/mainboard/tyan/s2735/Options.lb @@ -44,11 +44,13 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CROSS_COMPILE uses CC uses HOSTCC uses OBJCOPY +uses CONFIG_CHIP_NAME ### ### Build options diff --git a/src/mainboard/tyan/s2735/mainboard.c b/src/mainboard/tyan/s2735/mainboard.c index c2a68f341d..61ddd8242a 100644 --- a/src/mainboard/tyan/s2735/mainboard.c +++ b/src/mainboard/tyan/s2735/mainboard.c @@ -5,6 +5,8 @@ #include <device/pci_ops.h> #include "chip.h" +#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_tyan_s2735_ops = { CHIP_NAME("Tyan s2735 mainboard") }; +#endif diff --git a/src/mainboard/tyan/s2850/Config.lb b/src/mainboard/tyan/s2850/Config.lb index 761a55477c..ca890c8ded 100644 --- a/src/mainboard/tyan/s2850/Config.lb +++ b/src/mainboard/tyan/s2850/Config.lb @@ -121,7 +121,9 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc ## Include the secondary Configuration files ## dir /pc80 -config chip.h +if CONFIG_CHIP_NAME + config chip.h +end # sample config for tyan/s2850 chip northbridge/amd/amdk8/root_complex diff --git a/src/mainboard/tyan/s2850/mainboard.c b/src/mainboard/tyan/s2850/mainboard.c index 6ddd3e9727..8b96c5f0a6 100644 --- a/src/mainboard/tyan/s2850/mainboard.c +++ b/src/mainboard/tyan/s2850/mainboard.c @@ -5,6 +5,8 @@ #include <device/pci_ops.h> #include "chip.h" +#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_tyan_s2850_ops = { CHIP_NAME("Tyan s2850 mainboard") }; +#endif diff --git a/src/mainboard/tyan/s2875/Config.lb b/src/mainboard/tyan/s2875/Config.lb index ffc90a4d6c..7a27d7da7e 100644 --- a/src/mainboard/tyan/s2875/Config.lb +++ b/src/mainboard/tyan/s2875/Config.lb @@ -122,7 +122,9 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc ## Include the secondary Configuration files ## dir /pc80 -config chip.h +if CONFIG_CHIP_NAME + config chip.h +end # sample config for tyan/s2875 chip northbridge/amd/amdk8/root_complex diff --git a/src/mainboard/tyan/s2875/mainboard.c b/src/mainboard/tyan/s2875/mainboard.c index 81ce181e15..737178a492 100644 --- a/src/mainboard/tyan/s2875/mainboard.c +++ b/src/mainboard/tyan/s2875/mainboard.c @@ -5,6 +5,8 @@ #include <device/pci_ops.h> #include "chip.h" +#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_tyan_s2875_ops = { CHIP_NAME("Tyan s2875 mainboard") }; +#endif diff --git a/src/mainboard/tyan/s2880/Config.lb b/src/mainboard/tyan/s2880/Config.lb index 315e3b5e16..241e9d9968 100644 --- a/src/mainboard/tyan/s2880/Config.lb +++ b/src/mainboard/tyan/s2880/Config.lb @@ -122,7 +122,9 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc ## Include the secondary Configuration files ## dir /pc80 -config chip.h +if CONFIG_CHIP_NAME + config chip.h +end # sample config for tyan/s2880 chip northbridge/amd/amdk8/root_complex diff --git a/src/mainboard/tyan/s2880/mainboard.c b/src/mainboard/tyan/s2880/mainboard.c index b00bdfaa4a..535ccdc530 100644 --- a/src/mainboard/tyan/s2880/mainboard.c +++ b/src/mainboard/tyan/s2880/mainboard.c @@ -5,6 +5,8 @@ #include <device/pci_ops.h> #include "chip.h" +#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_tyan_s2880_ops = { CHIP_NAME("Tyan s2880 mainboard") }; +#endif diff --git a/src/mainboard/tyan/s2881/Config.lb b/src/mainboard/tyan/s2881/Config.lb index 17dcc90fa4..552324bc67 100644 --- a/src/mainboard/tyan/s2881/Config.lb +++ b/src/mainboard/tyan/s2881/Config.lb @@ -122,7 +122,9 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc ## Include the secondary Configuration files ## dir /pc80 -config chip.h +if CONFIG_CHIP_NAME + config chip.h +end # sample config for tyan/s2881 chip northbridge/amd/amdk8/root_complex diff --git a/src/mainboard/tyan/s2881/mainboard.c b/src/mainboard/tyan/s2881/mainboard.c index fb9b9c8b8a..e96bd39051 100644 --- a/src/mainboard/tyan/s2881/mainboard.c +++ b/src/mainboard/tyan/s2881/mainboard.c @@ -5,6 +5,8 @@ #include <device/pci_ops.h> #include "chip.h" +#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_tyan_s2881_ops = { CHIP_NAME("Tyan s2881 mainboard") }; +#endif diff --git a/src/mainboard/tyan/s2882/Config.lb b/src/mainboard/tyan/s2882/Config.lb index 7db07ad5e4..955432b05e 100644 --- a/src/mainboard/tyan/s2882/Config.lb +++ b/src/mainboard/tyan/s2882/Config.lb @@ -121,7 +121,9 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc ## Include the secondary Configuration files ## dir /pc80 -config chip.h +if CONFIG_CHIP_NAME + config chip.h +end # sample config for tyan/s2882 chip northbridge/amd/amdk8/root_complex diff --git a/src/mainboard/tyan/s2882/mainboard.c b/src/mainboard/tyan/s2882/mainboard.c index a910114263..8ad4bec92c 100644 --- a/src/mainboard/tyan/s2882/mainboard.c +++ b/src/mainboard/tyan/s2882/mainboard.c @@ -5,6 +5,8 @@ #include <device/pci_ops.h> #include "chip.h" +#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_tyan_s2882_ops = { CHIP_NAME("Tyan s2882 mainboard") }; +#endif diff --git a/src/mainboard/tyan/s2885/Config.lb b/src/mainboard/tyan/s2885/Config.lb index a07e068af5..3e8dd3beb9 100644 --- a/src/mainboard/tyan/s2885/Config.lb +++ b/src/mainboard/tyan/s2885/Config.lb @@ -125,7 +125,10 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc ## Include the secondary Configuration files ## dir /pc80 -config chip.h + +if CONFIG_CHIP_NAME + config chip.h +end # sample config for tyan/s2885 chip northbridge/amd/amdk8/root_complex diff --git a/src/mainboard/tyan/s2885/mainboard.c b/src/mainboard/tyan/s2885/mainboard.c index 3c7583dca9..1f652c2cca 100644 --- a/src/mainboard/tyan/s2885/mainboard.c +++ b/src/mainboard/tyan/s2885/mainboard.c @@ -5,6 +5,8 @@ #include <device/pci_ops.h> #include "chip.h" +#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_tyan_s2885_ops = { CHIP_NAME("Tyan s2885 mainboard") }; +#endif diff --git a/src/mainboard/tyan/s4880/Config.lb b/src/mainboard/tyan/s4880/Config.lb index d867537cf5..b9387cb700 100644 --- a/src/mainboard/tyan/s4880/Config.lb +++ b/src/mainboard/tyan/s4880/Config.lb @@ -121,7 +121,9 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc ## Include the secondary Configuration files ## dir /pc80 -config chip.h +if CONFIG_CHIP_NAME + config chip.h +end # sample config for tyan/s4880 chip northbridge/amd/amdk8/root_complex diff --git a/src/mainboard/tyan/s4880/mainboard.c b/src/mainboard/tyan/s4880/mainboard.c index fac83b534f..b13dd9f702 100644 --- a/src/mainboard/tyan/s4880/mainboard.c +++ b/src/mainboard/tyan/s4880/mainboard.c @@ -5,6 +5,8 @@ #include <device/pci_ops.h> #include "chip.h" +#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_tyan_s4880_ops = { CHIP_NAME("Tyan s4880 mainboard") }; +#endif diff --git a/src/mainboard/tyan/s4882/Config.lb b/src/mainboard/tyan/s4882/Config.lb index 0c17843628..27e14df397 100644 --- a/src/mainboard/tyan/s4882/Config.lb +++ b/src/mainboard/tyan/s4882/Config.lb @@ -121,7 +121,9 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc ## Include the secondary Configuration files ## dir /pc80 -config chip.h +if CONFIG_CHIP_NAME + config chip.h +end # sample config for tyan/s4882 chip northbridge/amd/amdk8/root_complex diff --git a/src/mainboard/tyan/s4882/mainboard.c b/src/mainboard/tyan/s4882/mainboard.c index 0277dd634f..9687ee313c 100644 --- a/src/mainboard/tyan/s4882/mainboard.c +++ b/src/mainboard/tyan/s4882/mainboard.c @@ -5,6 +5,8 @@ #include <device/pci_ops.h> #include "chip.h" +#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_tyan_s4882_ops = { CHIP_NAME("Tyan s4882 mainboard") }; +#endif diff --git a/src/northbridge/amd/amdk8/Config.lb b/src/northbridge/amd/amdk8/Config.lb index 2371e9b0e3..35b137068b 100644 --- a/src/northbridge/amd/amdk8/Config.lb +++ b/src/northbridge/amd/amdk8/Config.lb @@ -1,7 +1,11 @@ +uses CONFIG_CHIP_NAME uses AGP_APERTURE_SIZE default AGP_APERTURE_SIZE=0x4000000 -config chip.h +if CONFIG_CHIP_NAME + config chip.h +end + object northbridge.o driver misc_control.o diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index c58226915e..85f8fe4e86 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -488,12 +488,15 @@ static struct pci_driver mcf0_driver __pci_driver = { .device = 0x1100, }; +#if CONFIG_CHIP_NAME == 1 struct chip_operations northbridge_amd_amdk8_ops = { CHIP_NAME("AMD K8 Northbridge") .enable_dev = 0, }; +#endif + static void pci_domain_read_resources(device_t dev) { struct resource *resource; diff --git a/src/northbridge/intel/e7501/Config.lb b/src/northbridge/intel/e7501/Config.lb index f101a921fd..bce7a0b56e 100644 --- a/src/northbridge/intel/e7501/Config.lb +++ b/src/northbridge/intel/e7501/Config.lb @@ -1,4 +1,7 @@ -config chip.h -object northbridge.o -#driver misc_control.o +uses CONFIG_CHIP_NAME + +if CONFIG_CHIP_NAME + config chip.h +end +object northbridge.o diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c index ff65e29785..ec85be72a3 100644 --- a/src/northbridge/intel/e7501/northbridge.c +++ b/src/northbridge/intel/e7501/northbridge.c @@ -8,186 +8,8 @@ #include <bitops.h> #include "chip.h" -#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM) - -static void pci_domain_read_resources(device_t dev) -{ - struct resource *resource; - unsigned reg; - - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - resource->limit = 0xffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -} - -static void ram_resource(device_t dev, unsigned long index, - unsigned long basek, unsigned long sizek) -{ - struct resource *resource; - - if (!sizek) { - return; - } - resource = new_resource(dev, index); - resource->base = ((resource_t)basek) << 10; - resource->size = ((resource_t)sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - -static void tolm_test(void *gp, struct device *dev, struct resource *new) -{ - struct resource **best_p = gp; - struct resource *best; - best = *best_p; - if (!best || (best->base > new->base)) { - best = new; - } - *best_p = best; -} - -static uint32_t find_pci_tolm(struct bus *bus) -{ - struct resource *min; - uint32_t tolm; - min = 0; - search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); - tolm = 0xffffffffUL; - if (min && tolm > min->base) { - tolm = min->base; - } - return tolm; -} - -static void pci_domain_set_resources(device_t dev) -{ - struct resource *resource, *last; - device_t mc_dev; - uint32_t pci_tolm; - - pci_tolm = find_pci_tolm(&dev->link[0]); - mc_dev = dev->link[0].children; - if (mc_dev) { - /* Figure out which areas are/should be occupied by RAM. - * This is all computed in kilobytes and converted to/from - * the memory controller right at the edges. - * Having different variables in different units is - * too confusing to get right. Kilobytes are good up to - * 4 Terabytes of RAM... - */ - uint16_t tolm_r, remapbase_r, remaplimit_r; - unsigned long tomk, tolmk; - unsigned long remapbasek, remaplimitk; - int idx; - - /* Get the value of the highest DRB. This tells the end of - * the physical memory. The units are ticks of 64MB - * i.e. 1 means 64MB. - */ - tomk = ((unsigned long)pci_read_config8(mc_dev, 0x67)) << 16; - /* Compute the top of Low memory */ - tolmk = pci_tolm >> 10; - if (tolmk >= tomk) { - /* The PCI hole does not overlap memory - * we won't use the remap window. - */ - tolmk = tomk; - remapbasek = 0x3ff << 16; - remaplimitk = 0 << 16; - } - else { - /* The PCI memory hole overlaps memory - * setup the remap window. - */ - /* Find the bottom of the remap window - * is it above 4G? - */ - remapbasek = 4*1024*1024; - if (tomk > remapbasek) { - remapbasek = tomk; - } - /* Find the limit of the remap window */ - remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16)); - } - /* Write the ram configuration registers, - * preserving the reserved bits. - */ - tolm_r = pci_read_config16(mc_dev, 0xc4); - tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff); - pci_write_config16(mc_dev, 0xc4, tolm_r); - - remapbase_r = pci_read_config16(mc_dev, 0xc6); - remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00); - pci_write_config16(mc_dev, 0xc6, remapbase_r); - - remaplimit_r = pci_read_config16(mc_dev, 0xc8); - remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00); - pci_write_config16(mc_dev, 0xc8, remaplimit_r); - - /* Report the memory regions */ - idx = 10; - ram_resource(dev, idx++, 0, 640); - ram_resource(dev, idx++, 768, tolmk - 768); - if (tomk > 4*1024*1024) { - ram_resource(dev, idx++, 4096*1024, tomk - 4*1024*1024); - } - if (remaplimitk >= remapbasek) { - ram_resource(dev, idx++, remapbasek, - (remaplimitk + 64*1024) - remapbasek); - } - } - assign_resources(&dev->link[0]); -} - -static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) -{ - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); - return max; -} - -static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = enable_childrens_resources, - .init = 0, - .scan_bus = pci_domain_scan_bus, -}; - -static void cpu_bus_init(device_t dev) -{ - initialize_cpus(&dev->link[0]); -} - -static void cpu_bus_noop(device_t dev) -{ -} - -static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, - .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, - .scan_bus = 0, -}; - -static void enable_dev(struct device *dev) -{ - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { - dev->ops = &pci_domain_ops; - pci_set_method_conf1(); - } - else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { - dev->ops = &cpu_bus_ops; - } -} +#if CONFIG_CHIP_NAME struct chip_operations northbridge_intel_e7501_ops = { CHIP_NAME("Intel E7501 northbridge") - .enable_dev = enable_dev, }; +#endif diff --git a/src/northbridge/intel/e7501/root_complex/Config.lb b/src/northbridge/intel/e7501/root_complex/Config.lb new file mode 100644 index 0000000000..cd6db5c559 --- /dev/null +++ b/src/northbridge/intel/e7501/root_complex/Config.lb @@ -0,0 +1,2 @@ +config chip.h +object root_complex.o diff --git a/src/northbridge/intel/e7501/root_complex/chip.h b/src/northbridge/intel/e7501/root_complex/chip.h new file mode 100644 index 0000000000..a708dedc0c --- /dev/null +++ b/src/northbridge/intel/e7501/root_complex/chip.h @@ -0,0 +1,5 @@ +struct northbridge_intel_e7501_root_complex_config +{ +}; + +extern struct chip_operations northbridge_intel_e7501_root_complex_ops; diff --git a/src/northbridge/intel/e7501/root_complex/root_complex.c b/src/northbridge/intel/e7501/root_complex/root_complex.c new file mode 100644 index 0000000000..4e4dc5b3fe --- /dev/null +++ b/src/northbridge/intel/e7501/root_complex/root_complex.c @@ -0,0 +1,193 @@ +#include <console/console.h> +#include <arch/io.h> +#include <stdint.h> +#include <device/device.h> +#include <device/pci.h> +#include <stdlib.h> +#include <string.h> +#include <bitops.h> +#include "chip.h" + +#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM) + +static void pci_domain_read_resources(device_t dev) +{ + struct resource *resource; + unsigned reg; + + /* Initialize the system wide io space constraints */ + resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + + /* Initialize the system wide memory resources constraints */ + resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + resource->limit = 0xffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; +} + +static void ram_resource(device_t dev, unsigned long index, + unsigned long basek, unsigned long sizek) +{ + struct resource *resource; + + if (!sizek) { + return; + } + resource = new_resource(dev, index); + resource->base = ((resource_t)basek) << 10; + resource->size = ((resource_t)sizek) << 10; + resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; +} + +static void tolm_test(void *gp, struct device *dev, struct resource *new) +{ + struct resource **best_p = gp; + struct resource *best; + best = *best_p; + if (!best || (best->base > new->base)) { + best = new; + } + *best_p = best; +} + +static uint32_t find_pci_tolm(struct bus *bus) +{ + struct resource *min; + uint32_t tolm; + min = 0; + search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); + tolm = 0xffffffffUL; + if (min && tolm > min->base) { + tolm = min->base; + } + return tolm; +} + +static void pci_domain_set_resources(device_t dev) +{ + struct resource *resource, *last; + device_t mc_dev; + uint32_t pci_tolm; + + pci_tolm = find_pci_tolm(&dev->link[0]); + mc_dev = dev->link[0].children; + if (mc_dev) { + /* Figure out which areas are/should be occupied by RAM. + * This is all computed in kilobytes and converted to/from + * the memory controller right at the edges. + * Having different variables in different units is + * too confusing to get right. Kilobytes are good up to + * 4 Terabytes of RAM... + */ + uint16_t tolm_r, remapbase_r, remaplimit_r; + unsigned long tomk, tolmk; + unsigned long remapbasek, remaplimitk; + int idx; + + /* Get the value of the highest DRB. This tells the end of + * the physical memory. The units are ticks of 64MB + * i.e. 1 means 64MB. + */ + tomk = ((unsigned long)pci_read_config8(mc_dev, 0x67)) << 16; + /* Compute the top of Low memory */ + tolmk = pci_tolm >> 10; + if (tolmk >= tomk) { + /* The PCI hole does not overlap memory + * we won't use the remap window. + */ + tolmk = tomk; + remapbasek = 0x3ff << 16; + remaplimitk = 0 << 16; + } + else { + /* The PCI memory hole overlaps memory + * setup the remap window. + */ + /* Find the bottom of the remap window + * is it above 4G? + */ + remapbasek = 4*1024*1024; + if (tomk > remapbasek) { + remapbasek = tomk; + } + /* Find the limit of the remap window */ + remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16)); + } + /* Write the ram configuration registers, + * preserving the reserved bits. + */ + tolm_r = pci_read_config16(mc_dev, 0xc4); + tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff); + pci_write_config16(mc_dev, 0xc4, tolm_r); + + remapbase_r = pci_read_config16(mc_dev, 0xc6); + remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00); + pci_write_config16(mc_dev, 0xc6, remapbase_r); + + remaplimit_r = pci_read_config16(mc_dev, 0xc8); + remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00); + pci_write_config16(mc_dev, 0xc8, remaplimit_r); + + /* Report the memory regions */ + idx = 10; + ram_resource(dev, idx++, 0, 640); + ram_resource(dev, idx++, 768, tolmk - 768); + if (tomk > 4*1024*1024) { + ram_resource(dev, idx++, 4096*1024, tomk - 4*1024*1024); + } + if (remaplimitk >= remapbasek) { + ram_resource(dev, idx++, remapbasek, + (remaplimitk + 64*1024) - remapbasek); + } + } + assign_resources(&dev->link[0]); +} + +static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) +{ + max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); + return max; +} + +static struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = enable_childrens_resources, + .init = 0, + .scan_bus = pci_domain_scan_bus, +}; + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(&dev->link[0]); +} + +static void cpu_bus_noop(device_t dev) +{ +} + +static struct device_operations cpu_bus_ops = { + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, +}; + +static void enable_dev(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { + dev->ops = &pci_domain_ops; + pci_set_method_conf1(); + } + else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} +struct chip_operations northbridge_intel_e7501_root_complex_ops = { + CHIP_NAME("Intel E7501 Root Complex") + .enable_dev = enable_dev, +}; |