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-rw-r--r--src/arch/x86/acpi_s3.c2
-rw-r--r--src/arch/x86/c_start.S6
-rw-r--r--src/arch/x86/postcar_loader.c4
-rw-r--r--src/arch/x86/tables.c6
-rw-r--r--src/commonlib/include/commonlib/console/post_codes.h122
-rw-r--r--src/cpu/intel/car/core2/cache_as_ram.S4
-rw-r--r--src/cpu/intel/car/non-evict/cache_as_ram.S4
-rw-r--r--src/cpu/intel/car/p3/cache_as_ram.S4
-rw-r--r--src/cpu/intel/car/p4-netburst/cache_as_ram.S4
-rw-r--r--src/cpu/qemu-x86/cache_as_ram_bootblock.S4
-rw-r--r--src/cpu/x86/entry16.S2
-rw-r--r--src/cpu/x86/entry32.S2
-rw-r--r--src/device/device.c2
-rw-r--r--src/device/pci_device.c4
-rw-r--r--src/drivers/amd/agesa/cache_as_ram.S2
-rw-r--r--src/drivers/intel/fsp1_1/cache_as_ram.S6
-rw-r--r--src/drivers/intel/fsp1_1/car.c2
-rw-r--r--src/drivers/intel/fsp1_1/fsp_util.c4
-rw-r--r--src/drivers/intel/fsp1_1/raminit.c14
-rw-r--r--src/drivers/intel/fsp1_1/ramstage.c2
-rw-r--r--src/drivers/intel/fsp1_1/romstage.c2
-rw-r--r--src/drivers/intel/fsp2_0/memory_init.c12
-rw-r--r--src/drivers/intel/fsp2_0/notify.c12
-rw-r--r--src/drivers/intel/fsp2_0/silicon_init.c14
-rw-r--r--src/drivers/intel/fsp2_0/util.c2
-rw-r--r--src/drivers/pc80/rtc/post.c6
-rw-r--r--src/ec/google/wilco/commands.c4
-rw-r--r--src/lib/hardwaremain.c6
-rw-r--r--src/lib/prog_loaders.c10
-rw-r--r--src/lib/ramtest.c4
-rw-r--r--src/northbridge/intel/haswell/broadwell_mrc/raminit.c2
-rw-r--r--src/northbridge/intel/haswell/haswell_mrc/raminit.c4
-rw-r--r--src/northbridge/intel/i440bx/raminit.c8
-rw-r--r--src/northbridge/intel/sandybridge/raminit_mrc.c2
-rw-r--r--src/security/tpm/tspi/tspi.c2
-rw-r--r--src/security/vboot/vboot_logic.c2
-rw-r--r--src/soc/amd/cezanne/cpu.c2
-rw-r--r--src/soc/amd/common/block/cpu/car/cache_as_ram.S2
-rw-r--r--src/soc/amd/common/block/cpu/noncar/pre_c.S2
-rw-r--r--src/soc/amd/common/block/cpu/smm/finalize.c2
-rw-r--r--src/soc/amd/glinda/cpu.c2
-rw-r--r--src/soc/amd/mendocino/cpu.c2
-rw-r--r--src/soc/amd/phoenix/cpu.c2
-rw-r--r--src/soc/amd/picasso/cpu.c2
-rw-r--r--src/soc/amd/stoneyridge/cpu.c2
-rw-r--r--src/soc/intel/alderlake/finalize.c2
-rw-r--r--src/soc/intel/baytrail/romstage/raminit.c2
-rw-r--r--src/soc/intel/broadwell/finalize.c2
-rw-r--r--src/soc/intel/broadwell/raminit.c2
-rw-r--r--src/soc/intel/cannonlake/bootblock/pch.c2
-rw-r--r--src/soc/intel/cannonlake/finalize.c2
-rw-r--r--src/soc/intel/common/acpi/platform.asl4
-rw-r--r--src/soc/intel/common/block/cpu/car/cache_as_ram.S2
-rw-r--r--src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S4
-rw-r--r--src/soc/intel/common/block/graphics/graphics.c4
-rw-r--r--src/soc/intel/common/block/p2sb/p2sblib.c4
-rw-r--r--src/soc/intel/common/block/pmc/pmc.c2
-rw-r--r--src/soc/intel/elkhartlake/finalize.c2
-rw-r--r--src/soc/intel/jasperlake/finalize.c2
-rw-r--r--src/soc/intel/meteorlake/chip.c2
-rw-r--r--src/soc/intel/meteorlake/finalize.c2
-rw-r--r--src/soc/intel/skylake/finalize.c2
-rw-r--r--src/soc/intel/tigerlake/finalize.c2
-rw-r--r--src/soc/intel/xeon_sp/finalize.c2
-rw-r--r--src/southbridge/intel/common/finalize.c2
-rw-r--r--src/southbridge/intel/i82801gx/lpc.c2
-rw-r--r--src/vendorcode/google/chromeos/cr50_enable_update.c2
-rw-r--r--util/cbfstool/eventlog.c106
68 files changed, 234 insertions, 234 deletions
diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c
index ec1fafcd3c..f893e3a9f6 100644
--- a/src/arch/x86/acpi_s3.c
+++ b/src/arch/x86/acpi_s3.c
@@ -27,7 +27,7 @@ void __noreturn acpi_resume(void *wake_vec)
timestamp_add_now(TS_ACPI_WAKE_JUMP);
- post_code(POST_OS_RESUME);
+ post_code(POSTCODE_OS_RESUME);
acpi_do_wakeup((uintptr_t)wake_vec);
die("Failed the jump to wakeup vector\n");
diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
index 52aeb19b57..02ddf75d12 100644
--- a/src/arch/x86/c_start.S
+++ b/src/arch/x86/c_start.S
@@ -44,7 +44,7 @@ _start:
call SetCodeSelector
#endif
- post_code(POST_ENTRY_C_START) /* post 13 */
+ post_code(POSTCODE_ENTRY_C_START) /* post 13 */
cld
@@ -80,7 +80,7 @@ _start:
* bss is cleared. Now we call the main routine and
* let it do the rest.
*/
- post_code(POST_PRE_HARDWAREMAIN) /* post 6e */
+ post_code(POSTCODE_PRE_HARDWAREMAIN) /* post 6e */
andl $0xFFFFFFF0, %esp
@@ -95,7 +95,7 @@ _start:
call main
/* NOTREACHED */
.Lhlt:
- post_code(POST_DEAD_CODE) /* post ee */
+ post_code(POSTCODE_DEAD_CODE) /* post ee */
hlt
jmp .Lhlt
diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c
index 17286805ef..f8442d5d72 100644
--- a/src/arch/x86/postcar_loader.c
+++ b/src/arch/x86/postcar_loader.c
@@ -102,12 +102,12 @@ static void load_postcar_cbfs(struct prog *prog, struct postcar_frame *pcf)
vboot_run_logic();
if (rmodule_stage_load(&rsl))
- die_with_post_code(POST_INVALID_ROM,
+ die_with_post_code(POSTCODE_INVALID_ROM,
"Failed to load after CAR program.\n");
/* Set the stack pointer within parameters of the program loaded. */
if (rsl.params == NULL)
- die_with_post_code(POST_INVALID_ROM,
+ die_with_post_code(POSTCODE_INVALID_ROM,
"No parameters found in after CAR program.\n");
finalize_load(rsl.params, (uintptr_t)pcf->mtrr);
diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c
index b4b97b4677..1cff61436d 100644
--- a/src/arch/x86/tables.c
+++ b/src/arch/x86/tables.c
@@ -17,7 +17,7 @@ static unsigned long write_pirq_table(unsigned long rom_table_end)
unsigned long high_table_pointer;
#define MAX_PIRQ_TABLE_SIZE (4 * 1024)
- post_code(POST_X86_WRITE_PIRQ_TABLE);
+ post_code(POSTCODE_X86_WRITE_PIRQ_TABLE);
/* This table must be between 0x0f0000 and 0x100000 */
rom_table_end = write_pirq_routing_table(rom_table_end);
@@ -49,7 +49,7 @@ static unsigned long write_mptable(unsigned long rom_table_end)
unsigned long high_table_pointer;
#define MAX_MP_TABLE_SIZE (4 * 1024)
- post_code(POST_X86_WRITE_MPTABLE);
+ post_code(POSTCODE_X86_WRITE_MPTABLE);
/* The smp table must be in 0-1K, 639K-640K, or 960K-1M */
rom_table_end = write_smp_table(rom_table_end);
@@ -78,7 +78,7 @@ static unsigned long write_acpi_table(unsigned long rom_table_end)
unsigned long high_table_pointer;
const size_t max_acpi_size = CONFIG_MAX_ACPI_TABLE_SIZE_KB * KiB;
- post_code(POST_X86_WRITE_ACPITABLE);
+ post_code(POSTCODE_X86_WRITE_ACPITABLE);
/* Write ACPI tables to F segment and high tables area */
diff --git a/src/commonlib/include/commonlib/console/post_codes.h b/src/commonlib/include/commonlib/console/post_codes.h
index a8a8d953f6..0c96ee5155 100644
--- a/src/commonlib/include/commonlib/console/post_codes.h
+++ b/src/commonlib/include/commonlib/console/post_codes.h
@@ -31,7 +31,7 @@
* \brief Not an actual post-code - used to clear port80h
*
*/
-#define POST_CODE_CLEAR 0x00
+#define POSTCODE_CODE_CLEAR 0x00
/**
* \brief Entry into 'crt0.s'. reset code jumps to here
@@ -39,7 +39,7 @@
* First instruction that gets executed after the reset vector jumps.
* This indicates that the reset vector points to the correct code segment.
*/
-#define POST_RESET_VECTOR_CORRECT 0x01
+#define POSTCODE_RESET_VECTOR_CORRECT 0x01
/**
* \brief Entry into protected mode
@@ -47,14 +47,14 @@
* Preparing to enter protected mode. This is POSTed right before changing to
* protected mode.
*/
-#define POST_ENTER_PROTECTED_MODE 0x10
+#define POSTCODE_ENTER_PROTECTED_MODE 0x10
/**
* \brief Start copying coreboot to RAM with decompression if compressed
*
* POSTed before ramstage is about to be loaded into memory
*/
-#define POST_PREPARE_RAMSTAGE 0x11
+#define POSTCODE_PREPARE_RAMSTAGE 0x11
/**
* \brief Copy/decompression finished; jumping to RAM
@@ -62,34 +62,34 @@
* This is called after ramstage is loaded in memory, and before
* the code jumps there. This represents the end of romstage.
*/
-#define POST_RAMSTAGE_IS_PREPARED 0x12
+#define POSTCODE_RAMSTAGE_IS_PREPARED 0x12
/**
* \brief Entry into c_start
*
* c_start.S is the first code executing in ramstage.
*/
-#define POST_ENTRY_C_START 0x13
+#define POSTCODE_ENTRY_C_START 0x13
/**
* \brief Entry into bootblock cache-as-RAM code
*
*/
-#define POST_BOOTBLOCK_CAR 0x21
+#define POSTCODE_BOOTBLOCK_CAR 0x21
/**
* \brief Entry into pci_scan_bus
*
* Entered pci_scan_bus()
*/
-#define POST_ENTER_PCI_SCAN_BUS 0x24
+#define POSTCODE_ENTER_PCI_SCAN_BUS 0x24
/**
* \brief Entry into pci_scan_bus
*
* Entered pci_scan_bus()
*/
-#define POST_EXIT_PCI_SCAN_BUS 0x25
+#define POSTCODE_EXIT_PCI_SCAN_BUS 0x25
/**
* \brief Pre-memory init preparation start
@@ -97,7 +97,7 @@
* Post code emitted in romstage before making callbacks to allow SoC/mainboard
* to prepare params for FSP memory init.
*/
-#define POST_MEM_PREINIT_PREP_START 0x34
+#define POSTCODE_MEM_PREINIT_PREP_START 0x34
/**
* \brief Pre-memory init preparation end
@@ -105,14 +105,14 @@
* Post code emitted in romstage after returning from SoC/mainboard callbacks
* to prepare params for FSP memory init.
*/
-#define POST_MEM_PREINIT_PREP_END 0x36
+#define POSTCODE_MEM_PREINIT_PREP_END 0x36
/**
* \brief Console is initialized
*
* The console is initialized and is ready for usage
*/
-#define POST_CONSOLE_READY 0x39
+#define POSTCODE_CONSOLE_READY 0x39
/**
* \brief Console boot message succeeded
@@ -120,21 +120,21 @@
* First console message has been successfully sent through the console backend
* driver.
*/
-#define POST_CONSOLE_BOOT_MSG 0x40
+#define POSTCODE_CONSOLE_BOOT_MSG 0x40
/**
* \brief Before enabling the cache
*
* Going to enable the cache
*/
-#define POST_ENABLING_CACHE 0x60
+#define POSTCODE_ENABLING_CACHE 0x60
/**
* \brief Pre call to RAM stage main()
*
* POSTed right before RAM stage main() is called from c_start.S
*/
-#define POST_PRE_HARDWAREMAIN 0x6e
+#define POSTCODE_PRE_HARDWAREMAIN 0x6e
/**
* \brief Entry into coreboot in RAM stage main()
@@ -142,238 +142,238 @@
* This is the first call in hardwaremain.c. If this code is POSTed, then
* ramstage has successfully loaded and started executing.
*/
-#define POST_ENTRY_HARDWAREMAIN 0x6f
+#define POSTCODE_ENTRY_HARDWAREMAIN 0x6f
/**
* \brief Before Device Probe
*
* Boot State Machine: bs_pre_device()
*/
-#define POST_BS_PRE_DEVICE 0x70
+#define POSTCODE_BS_PRE_DEVICE 0x70
/**
* \brief Initializing Chips
*
* Boot State Machine: bs_dev_init_chips()
*/
-#define POST_BS_DEV_INIT_CHIPS 0x71
+#define POSTCODE_BS_DEV_INIT_CHIPS 0x71
/**
* \brief Starting Device Enumeration
*
* Boot State Machine: bs_dev_enumerate()
*/
-#define POST_BS_DEV_ENUMERATE 0x72
+#define POSTCODE_BS_DEV_ENUMERATE 0x72
/**
* \brief Device Resource Allocation
*
* Boot State Machine: bs_dev_resources()
*/
-#define POST_BS_DEV_RESOURCES 0x73
+#define POSTCODE_BS_DEV_RESOURCES 0x73
/**
* \brief Device Enable
*
* Boot State Machine: bs_dev_enable()
*/
-#define POST_BS_DEV_ENABLE 0x74
+#define POSTCODE_BS_DEV_ENABLE 0x74
/**
* \brief Device Initialization
*
* Boot State Machine: bs_dev_init()
*/
-#define POST_BS_DEV_INIT 0x75
+#define POSTCODE_BS_DEV_INIT 0x75
/**
* \brief After Device Probe
*
* Boot State Machine: bs_post_device()
*/
-#define POST_BS_POST_DEVICE 0x76
+#define POSTCODE_BS_POST_DEVICE 0x76
/**
* \brief OS Resume Check
*
* Boot State Machine: bs_os_resume_check()
*/
-#define POST_BS_OS_RESUME_CHECK 0x77
+#define POSTCODE_BS_OS_RESUME_CHECK 0x77
/**
* \brief OS Resume
*
* Boot State Machine: bs_os_resume()
*/
-#define POST_BS_OS_RESUME 0x78
+#define POSTCODE_BS_OS_RESUME 0x78
/**
* \brief Write Tables
*
* Boot State Machine: bs_write_tables()
*/
-#define POST_BS_WRITE_TABLES 0x79
+#define POSTCODE_BS_WRITE_TABLES 0x79
/**
* \brief Load Payload
*
* Boot State Machine: bs_payload_load()
*/
-#define POST_BS_PAYLOAD_LOAD 0x7a
+#define POSTCODE_BS_PAYLOAD_LOAD 0x7a
/**
* \brief Boot Payload
*
* Boot State Machine: bs_payload_boot()
*/
-#define POST_BS_PAYLOAD_BOOT 0x7b
+#define POSTCODE_BS_PAYLOAD_BOOT 0x7b
/**
* \brief Before calling FSP Notify (end of firmware)
*
* Going to call into FSP binary for Notify phase (end of firmware)
*/
-#define POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE 0x88
+#define POSTCODE_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE 0x88
/**
* \brief After calling FSP Notify (end of firmware)
*
* Going to call into FSP binary for Notify phase (end of firmware)
*/
-#define POST_FSP_NOTIFY_AFTER_END_OF_FIRMWARE 0x89
+#define POSTCODE_FSP_NOTIFY_AFTER_END_OF_FIRMWARE 0x89
/**
* \brief Before calling FSP TempRamInit
*
* Going to call into FSP binary for TempRamInit phase
*/
-#define POST_FSP_TEMP_RAM_INIT 0x90
+#define POSTCODE_FSP_TEMP_RAM_INIT 0x90
/**
* \brief Before calling FSP TempRamExit
*
* Going to call into FSP binary for TempRamExit phase
*/
-#define POST_FSP_TEMP_RAM_EXIT 0x91
+#define POSTCODE_FSP_TEMP_RAM_EXIT 0x91
/**
* \brief Before calling FSP MemoryInit
*
* Going to call into FSP binary for MemoryInit phase
*/
-#define POST_FSP_MEMORY_INIT 0x92
+#define POSTCODE_FSP_MEMORY_INIT 0x92
/**
* \brief Before calling FSP SiliconInit
*
* Going to call into FSP binary for SiliconInit phase
*/
-#define POST_FSP_SILICON_INIT 0x93
+#define POSTCODE_FSP_SILICON_INIT 0x93
/**
* \brief Before calling FSP Notify (after PCI enumeration)
*
* Going to call into FSP binary for Notify phase (after PCI enumeration)
*/
-#define POST_FSP_NOTIFY_BEFORE_ENUMERATE 0x94
+#define POSTCODE_FSP_NOTIFY_BEFORE_ENUMERATE 0x94
/**
* \brief Before calling FSP Notify (ready to boot)
*
* Going to call into FSP binary for Notify phase (ready to boot)
*/
-#define POST_FSP_NOTIFY_BEFORE_FINALIZE 0x95
+#define POSTCODE_FSP_NOTIFY_BEFORE_FINALIZE 0x95
/**
* \brief Indicate OS _PTS entry
*
* Called from _PTS asl method
*/
-#define POST_OS_ENTER_PTS 0x96
+#define POSTCODE_OS_ENTER_PTS 0x96
/**
* \brief Indicate OS _WAK entry
*
* Called from within _WAK method
*/
-#define POST_OS_ENTER_WAKE 0x97
+#define POSTCODE_OS_ENTER_WAKE 0x97
/**
* \brief After calling FSP MemoryInit
*
* FSP binary returned from MemoryInit phase
*/
-#define POST_FSP_MEMORY_EXIT 0x98
+#define POSTCODE_FSP_MEMORY_EXIT 0x98
/**
* \brief After calling FSP SiliconInit
*
* FSP binary returned from SiliconInit phase
*/
-#define POST_FSP_SILICON_EXIT 0x99
+#define POSTCODE_FSP_SILICON_EXIT 0x99
/**
* \brief Entry to write_pirq_table
*
* coreboot entered write_pirq_table
*/
-#define POST_X86_WRITE_PIRQ_TABLE 0x9a
+#define POSTCODE_X86_WRITE_PIRQ_TABLE 0x9a
/**
* \brief Entry to write_mptable
*
* coreboot entered write_mptable
*/
-#define POST_X86_WRITE_MPTABLE 0x9b
+#define POSTCODE_X86_WRITE_MPTABLE 0x9b
/**
* \brief Entry to write_acpi_table
*
* coreboot entered write_acpi_table
*/
-#define POST_X86_WRITE_ACPITABLE 0x9c
+#define POSTCODE_X86_WRITE_ACPITABLE 0x9c
/**
* \brief Before calling FSP Multiphase SiliconInit
*
* Going to call into FSP binary for Multiple phase SI Init
*/
-#define POST_FSP_MULTI_PHASE_SI_INIT_ENTRY 0xa0
+#define POSTCODE_FSP_MULTI_PHASE_SI_INIT_ENTRY 0xa0
/**
* \brief After calling FSP Multiphase SiliconInit
*
* FSP binary returned from Multiple phase SI Init
*/
-#define POST_FSP_MULTI_PHASE_SI_INIT_EXIT 0xa1
+#define POSTCODE_FSP_MULTI_PHASE_SI_INIT_EXIT 0xa1
/**
* \brief After calling FSP Notify (after PCI enumeration)
*
* Going to call into FSP binary for Notify phase (after PCI enumeration)
*/
-#define POST_FSP_NOTIFY_AFTER_ENUMERATE 0xa2
+#define POSTCODE_FSP_NOTIFY_AFTER_ENUMERATE 0xa2
/**
* \brief After calling FSP Notify (ready to boot)
*
* Going to call into FSP binary for Notify phase (ready to boot)
*/
-#define POST_FSP_NOTIFY_AFTER_FINALIZE 0xa3
+#define POSTCODE_FSP_NOTIFY_AFTER_FINALIZE 0xa3
/**
* \brief Invalid or corrupt ROM
*
* Set if firmware failed to find or validate a resource that is stored in ROM.
*/
-#define POST_INVALID_ROM 0xe0
+#define POSTCODE_INVALID_ROM 0xe0
/**
* \brief Invalid or corrupt CBFS
*
* Set if firmware failed to find or validate a resource that is stored in CBFS.
*/
-#define POST_INVALID_CBFS 0xe1
+#define POSTCODE_INVALID_CBFS 0xe1
/**
* \brief Vendor binary error
@@ -381,7 +381,7 @@
* Set if firmware failed to find or validate a vendor binary, or the binary
* generated a fatal error.
*/
-#define POST_INVALID_VENDOR_BINARY 0xe2
+#define POSTCODE_INVALID_VENDOR_BINARY 0xe2
/**
* \brief RAM failure
@@ -389,28 +389,28 @@
* Set if RAM could not be initialized. This includes RAM is missing,
* unsupported RAM configuration, or RAM failure.
*/
-#define POST_RAM_FAILURE 0xe3
+#define POSTCODE_RAM_FAILURE 0xe3
/**
* \brief Hardware initialization failure
*
* Set when a required hardware component was not found or is unsupported.
*/
-#define POST_HW_INIT_FAILURE 0xe4
+#define POSTCODE_HW_INIT_FAILURE 0xe4
/**
* \brief Video failure
*
* Video subsystem failed to initialize.
*/
-#define POST_VIDEO_FAILURE 0xe5
+#define POSTCODE_VIDEO_FAILURE 0xe5
/**
* \brief TPM failure
*
* An error with the TPM, either unexpected state or communications failure.
*/
-#define POST_TPM_FAILURE 0xed
+#define POSTCODE_TPM_FAILURE 0xed
/**
* \brief Not supposed to get here
@@ -419,7 +419,7 @@
*
* Check the console output for details.
*/
-#define POST_DEAD_CODE 0xee
+#define POSTCODE_DEAD_CODE 0xee
/**
* \brief Resume from suspend failed
@@ -427,7 +427,7 @@
* This post code is sent when the firmware is expected to resume it is
* unable to do so.
*/
-#define POST_RESUME_FAILURE 0xef
+#define POSTCODE_RESUME_FAILURE 0xef
/**
* \brief Jumping to payload
@@ -435,7 +435,7 @@
* Called right before jumping to a payload. If the boot sequence stops with
* this code, chances are the payload freezes.
*/
-#define POST_JUMPING_TO_PAYLOAD 0xf3
+#define POSTCODE_JUMPING_TO_PAYLOAD 0xf3
/**
* \brief Entry into elf boot
@@ -443,21 +443,21 @@
* This POST code is called right before invoking jmp_to_elf_entry()
* jmp_to_elf_entry() invokes the payload, and should never return
*/
-#define POST_ENTER_ELF_BOOT 0xf8
+#define POSTCODE_ENTER_ELF_BOOT 0xf8
/**
* \brief Final code before OS resumes
*
* Called right before jumping to the OS resume vector.
*/
-#define POST_OS_RESUME 0xfd
+#define POSTCODE_OS_RESUME 0xfd
/**
* \brief Final code before OS boots
*
* This may not be called depending on the payload used.
*/
-#define POST_OS_BOOT 0xfe
+#define POSTCODE_OS_BOOT 0xfe
/**
* \brief Elfload fail or die() called
@@ -474,6 +474,6 @@
* \n
* Check the console output to see exactly where the failure occurred.
*/
-#define POST_DIE 0xff
+#define POSTCODE_DIE 0xff
#endif /* POST_CODES_H */
diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S
index b9104e624e..316b703271 100644
--- a/src/cpu/intel/car/core2/cache_as_ram.S
+++ b/src/cpu/intel/car/core2/cache_as_ram.S
@@ -16,7 +16,7 @@ _cache_as_ram_setup:
bootblock_pre_c_entry:
cache_as_ram:
- post_code(POST_BOOTBLOCK_CAR)
+ post_code(POSTCODE_BOOTBLOCK_CAR)
/* Send INIT IPI to all excluding ourself. */
movl $0x000C4500, %eax
@@ -185,7 +185,7 @@ before_c_entry:
call bootblock_c_entry_bist
/* Should never see this postcode */
- post_code(POST_DEAD_CODE)
+ post_code(POSTCODE_DEAD_CODE)
.Lhlt:
hlt
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S
index d47fa725f1..187b1ca9e2 100644
--- a/src/cpu/intel/car/non-evict/cache_as_ram.S
+++ b/src/cpu/intel/car/non-evict/cache_as_ram.S
@@ -21,7 +21,7 @@ bootblock_pre_c_entry:
jmp check_mtrr /* Check if CPU properly reset */
cache_as_ram:
- post_code(POST_BOOTBLOCK_CAR)
+ post_code(POSTCODE_BOOTBLOCK_CAR)
/* Send INIT IPI to all excluding ourself. */
movl $0x000C4500, %eax
@@ -238,7 +238,7 @@ before_c_entry:
call bootblock_c_entry_bist
/* Should never see this postcode */
- post_code(POST_DEAD_CODE)
+ post_code(POSTCODE_DEAD_CODE)
.Lhlt:
diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S
index c19fa3cf6c..1431d323e6 100644
--- a/src/cpu/intel/car/p3/cache_as_ram.S
+++ b/src/cpu/intel/car/p3/cache_as_ram.S
@@ -14,7 +14,7 @@ _cache_as_ram_setup:
bootblock_pre_c_entry:
cache_as_ram:
- post_code(POST_BOOTBLOCK_CAR)
+ post_code(POSTCODE_BOOTBLOCK_CAR)
/* Clear/disable fixed MTRRs */
mov $fixed_mtrr_list_size, %ebx
@@ -160,7 +160,7 @@ before_c_entry:
call bootblock_c_entry_bist
/* Should never see this postcode */
- post_code(POST_DEAD_CODE)
+ post_code(POSTCODE_DEAD_CODE)
.Lhlt:
hlt
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index efd0d17d54..0362d104fa 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -20,7 +20,7 @@ _cache_as_ram_setup:
bootblock_pre_c_entry:
cache_as_ram:
- post_code(POST_BOOTBLOCK_CAR)
+ post_code(POSTCODE_BOOTBLOCK_CAR)
movl $LAPIC_BASE_MSR, %ecx
rdmsr
@@ -385,7 +385,7 @@ before_c_entry:
call bootblock_c_entry_bist
/* Should never see this postcode */
- post_code(POST_DEAD_CODE)
+ post_code(POSTCODE_DEAD_CODE)
.Lhlt:
hlt
diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S
index b414ca141f..fe872debea 100644
--- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S
+++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S
@@ -15,7 +15,7 @@
bootblock_pre_c_entry:
cache_as_ram:
- post_code(POST_BOOTBLOCK_CAR)
+ post_code(POSTCODE_BOOTBLOCK_CAR)
/*
* Nothing to do here on qemu, RAM works just fine without any
* initialization.
@@ -104,7 +104,7 @@ before_c_entry:
call bootblock_c_entry_bist
/* Never returns */
.Lhlt:
- post_code(POST_DEAD_CODE)
+ post_code(POSTCODE_DEAD_CODE)
hlt
jmp .Lhlt
diff --git a/src/cpu/x86/entry16.S b/src/cpu/x86/entry16.S
index d045c54937..ff4f1a26d0 100644
--- a/src/cpu/x86/entry16.S
+++ b/src/cpu/x86/entry16.S
@@ -43,7 +43,7 @@ _start16bit:
cli
/* Save the BIST result */
movl %eax, %ebp
- post_code(POST_RESET_VECTOR_CORRECT)
+ post_code(POSTCODE_RESET_VECTOR_CORRECT)
/* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before
* executing any further code. Even though paging is disabled we
diff --git a/src/cpu/x86/entry32.S b/src/cpu/x86/entry32.S
index 4c8ded0bc7..5c29581090 100644
--- a/src/cpu/x86/entry32.S
+++ b/src/cpu/x86/entry32.S
@@ -31,7 +31,7 @@ bootblock_protected_mode_entry:
/* Save the BIST value */
movl %eax, %ebp
- post_code(POST_ENTER_PROTECTED_MODE)
+ post_code(POSTCODE_ENTER_PROTECTED_MODE)
movw $ROM_DATA_SEG, %ax
movw %ax, %ds
diff --git a/src/device/device.c b/src/device/device.c
index ffda588d63..4cb0ec40cf 100644
--- a/src/device/device.c
+++ b/src/device/device.c
@@ -540,7 +540,7 @@ static void init_link(struct bus *link)
struct bus *c_link;
for (dev = link->children; dev; dev = dev->sibling) {
- post_code(POST_BS_DEV_INIT);
+ post_code(POSTCODE_BS_DEV_INIT);
post_log_path(dev);
init_dev(dev);
}
diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index 5c5a5fb8dc..60339e3ade 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -1438,7 +1438,7 @@ void pci_scan_bus(struct bus *bus, unsigned int min_devfn,
max_devfn=0xff;
}
- post_code(POST_ENTER_PCI_SCAN_BUS);
+ post_code(POSTCODE_ENTER_PCI_SCAN_BUS);
if (pci_bus_only_one_child(bus))
max_devfn = MIN(max_devfn, 0x07);
@@ -1529,7 +1529,7 @@ void pci_scan_bus(struct bus *bus, unsigned int min_devfn,
* side of any bridges that may be on this bus plus any devices.
* Return how far we've got finding sub-buses.
*/
- post_code(POST_EXIT_PCI_SCAN_BUS);
+ post_code(POSTCODE_EXIT_PCI_SCAN_BUS);
}
typedef enum {
diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S
index e3420397b1..9fd1a0aba2 100644
--- a/src/drivers/amd/agesa/cache_as_ram.S
+++ b/src/drivers/amd/agesa/cache_as_ram.S
@@ -64,7 +64,7 @@ bootblock_pre_c_entry:
/* Never reached. */
stop:
- post_code(POST_DEAD_CODE)
+ post_code(POSTCODE_DEAD_CODE)
hlt
jmp stop
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S
index 571feb4f92..17e0a69cd8 100644
--- a/src/drivers/intel/fsp1_1/cache_as_ram.S
+++ b/src/drivers/intel/fsp1_1/cache_as_ram.S
@@ -34,7 +34,7 @@ bootblock_pre_c_entry:
movd %eax, %mm1
cache_as_ram:
- post_code(POST_BOOTBLOCK_CAR)
+ post_code(POSTCODE_BOOTBLOCK_CAR)
/* Cache the rom and update the microcode */
cache_rom:
@@ -95,7 +95,7 @@ find_fsp_ret:
cmp $CONFIG_FSP_LOC, %eax
jbe halt1
- post_code(POST_FSP_TEMP_RAM_INIT)
+ post_code(POSTCODE_FSP_TEMP_RAM_INIT)
/* Calculate entry into FSP */
mov 0x30(%ebp), %eax /* Load TempRamInitEntry */
@@ -222,7 +222,7 @@ halt2:
#if CONFIG(POST_IO)
outb %al, $CONFIG_POST_IO_PORT
#else
- post_code(POST_DEAD_CODE)
+ post_code(POSTCODE_DEAD_CODE)
#endif
movl $LHLT_DELAY, %ecx
.Lhlt_Delay:
diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c
index fc05b91987..7455d30047 100644
--- a/src/drivers/intel/fsp1_1/car.c
+++ b/src/drivers/intel/fsp1_1/car.c
@@ -29,7 +29,7 @@ void mainboard_romstage_entry(void)
void *fsp = cbfs_map("fsp.bin", NULL);
if (!fsp)
- die_with_post_code(POST_INVALID_CBFS, "Unable to locate fsp.bin");
+ die_with_post_code(POSTCODE_INVALID_CBFS, "Unable to locate fsp.bin");
/* This leaks a mapping which this code assumes is benign as
* the flash is memory mapped CPU's address space. */
diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c
index 1c205ae24a..0d5faa8d3d 100644
--- a/src/drivers/intel/fsp1_1/fsp_util.c
+++ b/src/drivers/intel/fsp1_1/fsp_util.c
@@ -135,10 +135,10 @@ void fsp_notify(u32 phase)
if (phase == EnumInitPhaseReadyToBoot) {
timestamp_add_now(TS_FSP_FINALIZE_START);
- post_code(POST_FSP_NOTIFY_BEFORE_FINALIZE);
+ post_code(POSTCODE_FSP_NOTIFY_BEFORE_FINALIZE);
} else {
timestamp_add_now(TS_FSP_ENUMERATE_START);
- post_code(POST_FSP_NOTIFY_BEFORE_ENUMERATE);
+ post_code(POSTCODE_FSP_NOTIFY_BEFORE_ENUMERATE);
}
status = notify_phase_proc(&notify_phase_params);
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c
index 7da85d4a1c..dd35b0f228 100644
--- a/src/drivers/intel/fsp1_1/raminit.c
+++ b/src/drivers/intel/fsp1_1/raminit.c
@@ -50,7 +50,7 @@ void raminit(struct romstage_params *params)
* set to NULL. This indicates that the FSP code will use the UPD
* region in the FSP binary.
*/
- post_code(POST_MEM_PREINIT_PREP_START);
+ post_code(POSTCODE_MEM_PREINIT_PREP_START);
fsp_header = params->chipset_context;
vpd_ptr = (VPD_DATA_REGION *)(fsp_header->CfgRegionOffset +
fsp_header->ImageBase);
@@ -88,7 +88,7 @@ void raminit(struct romstage_params *params)
if (CONFIG(MMA))
setup_mma(&memory_init_params);
- post_code(POST_MEM_PREINIT_PREP_END);
+ post_code(POSTCODE_MEM_PREINIT_PREP_END);
/* Display the UPD data */
if (CONFIG(DISPLAY_UPD_DATA))
@@ -107,7 +107,7 @@ void raminit(struct romstage_params *params)
fsp_memory_init_params.HobListPtr);
timestamp_add_now(TS_FSP_MEMORY_INIT_START);
- post_code(POST_FSP_MEMORY_INIT);
+ post_code(POSTCODE_FSP_MEMORY_INIT);
status = fsp_memory_init(&fsp_memory_init_params);
mainboard_after_memory_init();
post_code(0x37);
@@ -115,7 +115,7 @@ void raminit(struct romstage_params *params)
printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status);
if (status != EFI_SUCCESS)
- die_with_post_code(POST_RAM_FAILURE,
+ die_with_post_code(POSTCODE_RAM_FAILURE,
"ERROR - FspMemoryInit failed to initialize memory!\n");
/* Locate the FSP reserved memory area */
@@ -172,7 +172,7 @@ void raminit(struct romstage_params *params)
}
if (hob_list_ptr == NULL)
- die_with_post_code(POST_RAM_FAILURE,
+ die_with_post_code(POSTCODE_RAM_FAILURE,
"ERROR - HOB pointer is NULL!\n");
/*
@@ -225,14 +225,14 @@ void raminit(struct romstage_params *params)
printk(BIOS_ERR,
"0x%08x: Chipset reserved bytes reported by FSP\n",
(unsigned int)delta_bytes);
- die_with_post_code(POST_INVALID_VENDOR_BINARY,
+ die_with_post_code(POSTCODE_INVALID_VENDOR_BINARY,
"Please verify the chipset reserved size\n");
}
}
/* Verify the FSP 1.1 HOB interface */
if (fsp_verification_failure)
- die_with_post_code(POST_INVALID_VENDOR_BINARY,
+ die_with_post_code(POSTCODE_INVALID_VENDOR_BINARY,
"ERROR - coreboot's requirements not met by FSP binary!\n");
/* Locate the memory configuration data to speed up the next reboot */
diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c
index a4b17bd037..200c89a8a9 100644
--- a/src/drivers/intel/fsp1_1/ramstage.c
+++ b/src/drivers/intel/fsp1_1/ramstage.c
@@ -93,7 +93,7 @@ static void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header)
timestamp_add_now(TS_FSP_SILICON_INIT_START);
printk(BIOS_DEBUG, "Calling FspSiliconInit(%p) at %p\n",
&silicon_init_params, fsp_silicon_init);
- post_code(POST_FSP_SILICON_INIT);
+ post_code(POSTCODE_FSP_SILICON_INIT);
status = fsp_silicon_init(&silicon_init_params);
timestamp_add_now(TS_FSP_SILICON_INIT_END);
printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status);
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index 3f93f33c50..dc890642a2 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -56,7 +56,7 @@ static void raminit_common(struct romstage_params *params)
printk(BIOS_DEBUG,
"No MRC cache "
"found in S3 resume path.\n");
- post_code(POST_RESUME_FAILURE);
+ post_code(POSTCODE_RESUME_FAILURE);
/* FIXME: A "system" reset is likely enough: */
full_reset();
} else {
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index 28e4d721ce..d6677b4732 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -260,7 +260,7 @@ static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake)
const struct fsp_header *hdr = &context->header;
const struct memranges *memmap = &context->memmap;
- post_code(POST_MEM_PREINIT_PREP_START);
+ post_code(POSTCODE_MEM_PREINIT_PREP_START);
if (CONFIG(MRC_CACHE_USING_MRC_VERSION))
version = fsp_mrc_version();
@@ -299,7 +299,7 @@ static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake)
/* Fill common settings on behalf of chipset. */
if (fsp_fill_common_arch_params(arch_upd, s3wake, version,
memmap) != CB_SUCCESS)
- die_with_post_code(POST_INVALID_VENDOR_BINARY,
+ die_with_post_code(POSTCODE_INVALID_VENDOR_BINARY,
"FSPM_ARCH_UPD not found!\n");
/* Early caching of RAMTOP region if valid mrc cache data is found */
@@ -324,7 +324,7 @@ static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake)
if (CONFIG(MMA))
setup_mma(&fspm_upd.FspmConfig);
- post_code(POST_MEM_PREINIT_PREP_END);
+ post_code(POSTCODE_MEM_PREINIT_PREP_END);
/* Call FspMemoryInit */
fsp_raminit = (void *)(uintptr_t)(hdr->image_base + hdr->fsp_memory_init_entry_offset);
@@ -332,7 +332,7 @@ static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake)
/* FSP disables the interrupt handler so remove debug exceptions temporarily */
null_breakpoint_disable();
- post_code(POST_FSP_MEMORY_INIT);
+ post_code(POSTCODE_FSP_MEMORY_INIT);
timestamp_add_now(TS_FSP_MEMORY_INIT_START);
if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32))
status = protected_mode_call_2arg(fsp_raminit,
@@ -342,13 +342,13 @@ static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake)
status = fsp_raminit(&fspm_upd, fsp_get_hob_list_ptr());
null_breakpoint_init();
- post_code(POST_FSP_MEMORY_EXIT);
+ post_code(POSTCODE_FSP_MEMORY_EXIT);
timestamp_add_now(TS_FSP_MEMORY_INIT_END);
/* Handle any errors returned by FspMemoryInit */
fsp_handle_reset(status);
if (status != FSP_SUCCESS) {
- die_with_post_code(POST_RAM_FAILURE,
+ die_with_post_code(POSTCODE_RAM_FAILURE,
"FspMemoryInit returned with error 0x%08x!\n", status);
}
diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c
index 44e8795d91..22bbf539d3 100644
--- a/src/drivers/intel/fsp2_0/notify.c
+++ b/src/drivers/intel/fsp2_0/notify.c
@@ -22,24 +22,24 @@ static const struct fsp_notify_phase_data notify_data[] = {
{
.notify_phase = AFTER_PCI_ENUM,
.skip = !CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM),
- .post_code_before = POST_FSP_NOTIFY_BEFORE_ENUMERATE,
- .post_code_after = POST_FSP_NOTIFY_AFTER_ENUMERATE,
+ .post_code_before = POSTCODE_FSP_NOTIFY_BEFORE_ENUMERATE,
+ .post_code_after = POSTCODE_FSP_NOTIFY_AFTER_ENUMERATE,
.timestamp_before = TS_FSP_ENUMERATE_START,
.timestamp_after = TS_FSP_ENUMERATE_END,
},
{
.notify_phase = READY_TO_BOOT,
.skip = !CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT),
- .post_code_before = POST_FSP_NOTIFY_BEFORE_FINALIZE,
- .post_code_after = POST_FSP_NOTIFY_AFTER_FINALIZE,
+ .post_code_before = POSTCODE_FSP_NOTIFY_BEFORE_FINALIZE,
+ .post_code_after = POSTCODE_FSP_NOTIFY_AFTER_FINALIZE,
.timestamp_before = TS_FSP_FINALIZE_START,
.timestamp_after = TS_FSP_FINALIZE_END,
},
{
.notify_phase = END_OF_FIRMWARE,
.skip = !CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE),
- .post_code_before = POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE,
- .post_code_after = POST_FSP_NOTIFY_AFTER_END_OF_FIRMWARE,
+ .post_code_before = POSTCODE_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE,
+ .post_code_after = POSTCODE_FSP_NOTIFY_AFTER_END_OF_FIRMWARE,
.timestamp_before = TS_FSP_END_OF_FIRMWARE_START,
.timestamp_after = TS_FSP_END_OF_FIRMWARE_END,
},
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index 9505e1d56f..72a30c51e3 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -52,9 +52,9 @@ static void fsps_return_value_handler(enum fsp_silicon_init_phases phases, uint3
/* Handle all other errors returned by FSP-S APIs */
/* Assume video failure if attempted to initialize graphics */
if (CONFIG(RUN_FSP_GOP) && vbt_get())
- postcode = POST_VIDEO_FAILURE;
+ postcode = POSTCODE_VIDEO_FAILURE;
else
- postcode = POST_HW_INIT_FAILURE; /* else generic */
+ postcode = POSTCODE_HW_INIT_FAILURE; /* else generic */
switch (phases) {
case FSP_SILICON_INIT_API:
@@ -108,7 +108,7 @@ static void do_silicon_init(struct fsp_header *hdr)
* don't leave it like this as FSP default settings can be bad choices for coreboot.
*/
if (!hdr->cfg_region_size || hdr->cfg_region_size < sizeof(FSPS_UPD))
- die_with_post_code(POST_INVALID_VENDOR_BINARY,
+ die_with_post_code(POSTCODE_INVALID_VENDOR_BINARY,
"Invalid FSPS UPD region\n");
else if (hdr->cfg_region_size > sizeof(FSPS_UPD))
printk(BIOS_ERR, "FSP and coreboot are out of sync! FSPS UPD size > coreboot\n");
@@ -133,7 +133,7 @@ static void do_silicon_init(struct fsp_header *hdr)
fsp_debug_before_silicon_init(silicon_init, supd, upd);
timestamp_add_now(TS_FSP_SILICON_INIT_START);
- post_code(POST_FSP_SILICON_INIT);
+ post_code(POSTCODE_FSP_SILICON_INIT);
/* FSP disables the interrupt handler so remove debug exceptions temporarily */
null_breakpoint_disable();
@@ -146,7 +146,7 @@ static void do_silicon_init(struct fsp_header *hdr)
printk(BIOS_INFO, "FSPS returned %x\n", status);
timestamp_add_now(TS_FSP_SILICON_INIT_END);
- post_code(POST_FSP_SILICON_EXIT);
+ post_code(POSTCODE_FSP_SILICON_EXIT);
if (CONFIG(BMP_LOGO))
bmp_release_logo();
@@ -173,7 +173,7 @@ static void do_silicon_init(struct fsp_header *hdr)
if (multi_phase_si_init == NULL)
return;
- post_code(POST_FSP_MULTI_PHASE_SI_INIT_ENTRY);
+ post_code(POSTCODE_FSP_MULTI_PHASE_SI_INIT_ENTRY);
timestamp_add_now(TS_FSP_MULTI_PHASE_SI_INIT_START);
/* Get NumberOfPhases Value */
multi_phase_params.multi_phase_action = GET_NUMBER_OF_PHASES;
@@ -200,7 +200,7 @@ static void do_silicon_init(struct fsp_header *hdr)
fsps_return_value_handler(FSP_MULTI_PHASE_SI_INIT_EXECUTE_PHASE_API, status);
}
timestamp_add_now(TS_FSP_MULTI_PHASE_SI_INIT_END);
- post_code(POST_FSP_MULTI_PHASE_SI_INIT_EXIT);
+ post_code(POSTCODE_FSP_MULTI_PHASE_SI_INIT_EXIT);
}
static void *fsps_allocator(void *arg_unused, size_t size, const union cbfs_mdata *mdata_unused)
diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c
index 7fa2af4722..f912d9acab 100644
--- a/src/drivers/intel/fsp2_0/util.c
+++ b/src/drivers/intel/fsp2_0/util.c
@@ -182,7 +182,7 @@ void fsp_verify_upd_header_signature(uint64_t upd_signature, uint64_t expected_s
if (upd_signature != expected_signature) {
/* The UPD signatures are non-zero-terminated ASCII stored as a little endian
uint64_t, so this needs some casts. */
- die_with_post_code(POST_INVALID_VENDOR_BINARY,
+ die_with_post_code(POSTCODE_INVALID_VENDOR_BINARY,
"Invalid UPD signature! FSP provided \"%.8s\", expected was \"%.8s\".\n",
(char *)&upd_signature,
(char *)&expected_signature);
diff --git a/src/drivers/pc80/rtc/post.c b/src/drivers/pc80/rtc/post.c
index aa8ea18ee9..8150fbad8a 100644
--- a/src/drivers/pc80/rtc/post.c
+++ b/src/drivers/pc80/rtc/post.c
@@ -60,9 +60,9 @@ int cmos_post_previous_boot(u8 *code, u32 *extra)
/* Check last post code in previous boot against normal list */
switch (*code) {
- case POST_OS_BOOT:
- case POST_OS_RESUME:
- case POST_ENTER_ELF_BOOT:
+ case POSTCODE_OS_BOOT:
+ case POSTCODE_OS_RESUME:
+ case POSTCODE_ENTER_ELF_BOOT:
case 0:
break;
default:
diff --git a/src/ec/google/wilco/commands.c b/src/ec/google/wilco/commands.c
index 98b1efb581..93f66332f1 100644
--- a/src/ec/google/wilco/commands.c
+++ b/src/ec/google/wilco/commands.c
@@ -179,8 +179,8 @@ struct err_code_entry {
*/
static const enum ec_err_code default_ec_err = DLED_ROM;
static const struct err_code_entry post_code_err_map[] = {
- { .post_code = POST_RAM_FAILURE, .ec_err = DLED_MEMORY, },
- { .post_code = POST_VIDEO_FAILURE, .ec_err = DLED_PANEL, },
+ { .post_code = POSTCODE_RAM_FAILURE, .ec_err = DLED_MEMORY, },
+ { .post_code = POSTCODE_VIDEO_FAILURE, .ec_err = DLED_PANEL, },
};
/* Records the most recent post code during boot */
diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c
index 47022ac858..cee48ab8f2 100644
--- a/src/lib/hardwaremain.c
+++ b/src/lib/hardwaremain.c
@@ -60,7 +60,7 @@ struct boot_state {
{ \
.name = #state_, \
.id = state_, \
- .post_code = POST_ ## state_, \
+ .post_code = POSTCODE_ ## state_, \
.phases = { { NULL, 0 }, { NULL, 0 } }, \
.run_state = run_func_, \
.arg = NULL, \
@@ -444,7 +444,7 @@ void main(void)
/* console_init() MUST PRECEDE ALL printk()! Additionally, ensure
* it is the very first thing done in ramstage.*/
console_init();
- post_code(POST_CONSOLE_READY);
+ post_code(POSTCODE_CONSOLE_READY);
exception_init();
@@ -455,7 +455,7 @@ void main(void)
cbmem_initialize();
timestamp_add_now(TS_RAMSTAGE_START);
- post_code(POST_ENTRY_HARDWAREMAIN);
+ post_code(POSTCODE_ENTRY_HARDWAREMAIN);
/* Handoff sleep type from romstage. */
acpi_is_wakeup_s3();
diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c
index 08ba66a0c5..17d946eac9 100644
--- a/src/lib/prog_loaders.c
+++ b/src/lib/prog_loaders.c
@@ -39,7 +39,7 @@ void run_romstage(void)
fail:
if (CONFIG(BOOTBLOCK_CONSOLE))
- die_with_post_code(POST_INVALID_ROM,
+ die_with_post_code(POSTCODE_INVALID_ROM,
"Couldn't load romstage.\n");
halt();
}
@@ -123,7 +123,7 @@ void __noreturn run_ramstage(void)
prog_run(&ramstage);
fail:
- die_with_post_code(POST_INVALID_ROM, "Ramstage was not loaded!\n");
+ die_with_post_code(POSTCODE_INVALID_ROM, "Ramstage was not loaded!\n");
}
#if ENV_PAYLOAD_LOADER // gc-sections should take care of this
@@ -166,7 +166,7 @@ void payload_load(void)
}
__fallthrough;
default:
- die_with_post_code(POST_INVALID_ROM,
+ die_with_post_code(POSTCODE_INVALID_ROM,
"Unsupported payload type %d.\n", payload->cbfs_type);
break;
}
@@ -174,7 +174,7 @@ void payload_load(void)
cbfs_unmap(mapping);
out:
if (prog_entry(payload) == NULL)
- die_with_post_code(POST_INVALID_ROM, "Payload not loaded.\n");
+ die_with_post_code(POSTCODE_INVALID_ROM, "Payload not loaded.\n");
}
void payload_run(void)
@@ -187,7 +187,7 @@ void payload_run(void)
printk(BIOS_DEBUG, "Jumping to boot code at %p(%p)\n",
prog_entry(payload), prog_entry_arg(payload));
- post_code(POST_ENTER_ELF_BOOT);
+ post_code(POSTCODE_ENTER_ELF_BOOT);
timestamp_add_now(TS_SELFBOOT_JUMP);
diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c
index a3b2528878..90fc777a25 100644
--- a/src/lib/ramtest.c
+++ b/src/lib/ramtest.c
@@ -110,7 +110,7 @@ static int ram_bitset_nodie(uintptr_t start)
}
}
if (failures) {
- post_code(POST_RAM_FAILURE);
+ post_code(POSTCODE_RAM_FAILURE);
printk(BIOS_DEBUG, "\nDRAM did _NOT_ verify!\n");
return 1;
}
@@ -200,7 +200,7 @@ void quick_ram_check_or_die(uintptr_t dst)
write_phys(dst, backup);
if (fail) {
- post_code(POST_RAM_FAILURE);
+ post_code(POSTCODE_RAM_FAILURE);
die("RAM INIT FAILURE!\n");
}
phys_memory_barrier();
diff --git a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
index 28422fb296..ae4459a7e0 100644
--- a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
+++ b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
@@ -119,7 +119,7 @@ static void sdram_initialize(struct pei_data *pei_data)
/* Waking from S3 and no cache. */
printk(BIOS_DEBUG,
"No MRC cache found in S3 resume path.\n");
- post_code(POST_RESUME_FAILURE);
+ post_code(POSTCODE_RESUME_FAILURE);
system_reset();
} else {
printk(BIOS_DEBUG, "No MRC cache found.\n");
diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
index 7adae9e64c..bf072fa955 100644
--- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c
+++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
@@ -125,7 +125,7 @@ static void sdram_initialize(struct pei_data *pei_data)
/* If MRC data is not found, we cannot continue S3 resume */
if (pei_data->boot_mode == 2 && !pei_data->mrc_input) {
- post_code(POST_RESUME_FAILURE);
+ post_code(POSTCODE_RESUME_FAILURE);
printk(BIOS_DEBUG, "Giving up in %s: No MRC data\n", __func__);
system_reset();
}
@@ -157,7 +157,7 @@ static void sdram_initialize(struct pei_data *pei_data)
default:
printk(BIOS_ERR, "MRC returned %x.\n", rv);
}
- die_with_post_code(POST_INVALID_VENDOR_BINARY,
+ die_with_post_code(POSTCODE_INVALID_VENDOR_BINARY,
"Nonzero MRC return value.\n");
}
} else {
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index 3c0951df08..ec93563699 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -764,7 +764,7 @@ static void set_dram_row_attributes(void)
PRINT_DEBUG("Found DIMM in slot %d\n", i);
if (edo && sd) {
- die_with_post_code(POST_RAM_FAILURE,
+ die_with_post_code(POSTCODE_RAM_FAILURE,
"Mixing EDO/SDRAM unsupported!\n");
}
@@ -869,11 +869,11 @@ static void set_dram_row_attributes(void)
if (col == 4)
bpr |= 0xc0;
} else {
- die_with_post_code(POST_RAM_FAILURE,
+ die_with_post_code(POSTCODE_RAM_FAILURE,
"# of banks of DIMM unsupported!\n");
}
if (dra == -1) {
- die_with_post_code(POST_RAM_FAILURE,
+ die_with_post_code(POSTCODE_RAM_FAILURE,
"Page size not supported!\n");
}
@@ -884,7 +884,7 @@ static void set_dram_row_attributes(void)
*/
struct dimm_size sz = spd_get_dimm_size(device);
if ((sz.side1 < 8)) {
- die_with_post_code(POST_RAM_FAILURE,
+ die_with_post_code(POSTCODE_RAM_FAILURE,
"DIMMs smaller than 8MB per side "
"are not supported!\n");
}
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index a2a44c422e..816fe318c2 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -168,7 +168,7 @@ static void sdram_initialize(struct pei_data *pei_data)
default:
printk(BIOS_ERR, "MRC returned %x.\n", rv);
}
- die_with_post_code(POST_INVALID_VENDOR_BINARY,
+ die_with_post_code(POSTCODE_INVALID_VENDOR_BINARY,
"Nonzero MRC return value.\n");
}
} else {
diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c
index a771d2a736..ec695819fd 100644
--- a/src/security/tpm/tspi/tspi.c
+++ b/src/security/tpm/tspi/tspi.c
@@ -81,7 +81,7 @@ static uint32_t tpm_setup_s3_helper(void)
static uint32_t tpm_setup_epilogue(uint32_t result)
{
if (result != TPM_SUCCESS)
- post_code(POST_TPM_FAILURE);
+ post_code(POSTCODE_TPM_FAILURE);
else
printk(BIOS_INFO, "TPM: setup succeeded\n");
diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c
index 650a420bad..53314b2143 100644
--- a/src/security/vboot/vboot_logic.c
+++ b/src/security/vboot/vboot_logic.c
@@ -345,7 +345,7 @@ void verstage_main(void)
struct region_device fw_body;
rv = vboot_locate_firmware(ctx, &fw_body);
if (rv)
- die_with_post_code(POST_INVALID_ROM,
+ die_with_post_code(POSTCODE_INVALID_ROM,
"Failed to read FMAP to locate firmware");
rv = hash_body(ctx, &fw_body);
diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c
index 9261d54f87..c1cf663336 100644
--- a/src/soc/amd/cezanne/cpu.c
+++ b/src/soc/amd/cezanne/cpu.c
@@ -22,7 +22,7 @@ void mp_init_cpus(struct bus *cpu_bus)
{
extern const struct mp_ops amd_mp_ops_with_smm;
if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS)
- die_with_post_code(POST_HW_INIT_FAILURE,
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"mp_init_with_smm failed. Halting.\n");
/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S
index b38ce80895..372f51517b 100644
--- a/src/soc/amd/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S
@@ -48,7 +48,7 @@ before_carstage:
/* Never reached */
.halt_forever:
- post_code(POST_DEAD_CODE)
+ post_code(POSTCODE_DEAD_CODE)
hlt
jmp .halt_forever
diff --git a/src/soc/amd/common/block/cpu/noncar/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S
index e123c361cc..72d778886a 100644
--- a/src/soc/amd/common/block/cpu/noncar/pre_c.S
+++ b/src/soc/amd/common/block/cpu/noncar/pre_c.S
@@ -63,6 +63,6 @@ bootblock_pre_c_entry:
/* Never reached */
.halt_forever:
- post_code(POST_DEAD_CODE)
+ post_code(POSTCODE_DEAD_CODE)
hlt
jmp .halt_forever
diff --git a/src/soc/amd/common/block/cpu/smm/finalize.c b/src/soc/amd/common/block/cpu/smm/finalize.c
index a6d9a739f4..b81b9bcd1d 100644
--- a/src/soc/amd/common/block/cpu/smm/finalize.c
+++ b/src/soc/amd/common/block/cpu/smm/finalize.c
@@ -20,7 +20,7 @@ static void soc_finalize(void *unused)
acpi_enable_sci();
}
- post_code(POST_OS_BOOT);
+ post_code(POSTCODE_OS_BOOT);
}
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
diff --git a/src/soc/amd/glinda/cpu.c b/src/soc/amd/glinda/cpu.c
index 49cd11cdbf..f780f2193d 100644
--- a/src/soc/amd/glinda/cpu.c
+++ b/src/soc/amd/glinda/cpu.c
@@ -25,7 +25,7 @@ void mp_init_cpus(struct bus *cpu_bus)
{
extern const struct mp_ops amd_mp_ops_with_smm;
if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS)
- die_with_post_code(POST_HW_INIT_FAILURE,
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"mp_init_with_smm failed. Halting.\n");
/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
diff --git a/src/soc/amd/mendocino/cpu.c b/src/soc/amd/mendocino/cpu.c
index c742db0e75..5d6bb169d7 100644
--- a/src/soc/amd/mendocino/cpu.c
+++ b/src/soc/amd/mendocino/cpu.c
@@ -23,7 +23,7 @@ void mp_init_cpus(struct bus *cpu_bus)
{
extern const struct mp_ops amd_mp_ops_with_smm;
if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS)
- die_with_post_code(POST_HW_INIT_FAILURE,
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"mp_init_with_smm failed. Halting.\n");
/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
diff --git a/src/soc/amd/phoenix/cpu.c b/src/soc/amd/phoenix/cpu.c
index 2c8f77130a..19327776d9 100644
--- a/src/soc/amd/phoenix/cpu.c
+++ b/src/soc/amd/phoenix/cpu.c
@@ -25,7 +25,7 @@ void mp_init_cpus(struct bus *cpu_bus)
{
extern const struct mp_ops amd_mp_ops_with_smm;
if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS)
- die_with_post_code(POST_HW_INIT_FAILURE,
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"mp_init_with_smm failed. Halting.\n");
/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c
index c0b918e5c0..be767dcd18 100644
--- a/src/soc/amd/picasso/cpu.c
+++ b/src/soc/amd/picasso/cpu.c
@@ -22,7 +22,7 @@ void mp_init_cpus(struct bus *cpu_bus)
{
extern const struct mp_ops amd_mp_ops_with_smm;
if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS)
- die_with_post_code(POST_HW_INIT_FAILURE,
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"mp_init_with_smm failed. Halting.\n");
/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c
index 3aedd0eb88..f2df3cecde 100644
--- a/src/soc/amd/stoneyridge/cpu.c
+++ b/src/soc/amd/stoneyridge/cpu.c
@@ -24,7 +24,7 @@ void mp_init_cpus(struct bus *cpu_bus)
{
extern const struct mp_ops amd_mp_ops_with_smm;
if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS)
- die_with_post_code(POST_HW_INIT_FAILURE,
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"mp_init_with_smm failed. Halting.\n");
/* The flash is now no longer cacheable. Reset to WP for performance. */
diff --git a/src/soc/intel/alderlake/finalize.c b/src/soc/intel/alderlake/finalize.c
index 2900045a66..460c8af174 100644
--- a/src/soc/intel/alderlake/finalize.c
+++ b/src/soc/intel/alderlake/finalize.c
@@ -91,7 +91,7 @@ static void soc_finalize(void *unused)
heci_finalize();
/* Indicate finalize step with post code */
- post_code(POST_OS_BOOT);
+ post_code(POSTCODE_OS_BOOT);
}
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c
index 79614afc16..b64364bed8 100644
--- a/src/soc/intel/baytrail/romstage/raminit.c
+++ b/src/soc/intel/baytrail/romstage/raminit.c
@@ -146,7 +146,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
} else if (s3resume) {
/* If waking from S3 and no cache then. */
printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n");
- post_code(POST_RESUME_FAILURE);
+ post_code(POSTCODE_RESUME_FAILURE);
system_reset();
} else {
printk(BIOS_DEBUG, "No MRC cache found.\n");
diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c
index 20bb18736d..d71ac0996d 100644
--- a/src/soc/intel/broadwell/finalize.c
+++ b/src/soc/intel/broadwell/finalize.c
@@ -58,7 +58,7 @@ static void broadwell_finalize(void *unused)
broadwell_pch_finalize();
/* Indicate finalize step with post code */
- post_code(POST_OS_BOOT);
+ post_code(POSTCODE_OS_BOOT);
}
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, broadwell_finalize, NULL);
diff --git a/src/soc/intel/broadwell/raminit.c b/src/soc/intel/broadwell/raminit.c
index d088e5145c..c55e755055 100644
--- a/src/soc/intel/broadwell/raminit.c
+++ b/src/soc/intel/broadwell/raminit.c
@@ -102,7 +102,7 @@ static void sdram_initialize(struct pei_data *pei_data)
/* Waking from S3 and no cache. */
printk(BIOS_DEBUG,
"No MRC cache found in S3 resume path.\n");
- post_code(POST_RESUME_FAILURE);
+ post_code(POSTCODE_RESUME_FAILURE);
system_reset();
} else {
printk(BIOS_DEBUG, "No MRC cache found.\n");
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index 9df4ac35b9..837f1573f8 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -84,7 +84,7 @@ static void soc_config_acpibase(void)
pmc_base_reg = get_pmc_reg_base();
if (!pmc_base_reg)
- die_with_post_code(POST_HW_INIT_FAILURE,
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"Invalid PMC base address\n");
pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg +
diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c
index e45ae9ae98..ba7fc69b55 100644
--- a/src/soc/intel/cannonlake/finalize.c
+++ b/src/soc/intel/cannonlake/finalize.c
@@ -93,7 +93,7 @@ static void soc_finalize(void *unused)
heci1_disable();
/* Indicate finalize step with post code */
- post_code(POST_OS_BOOT);
+ post_code(POSTCODE_OS_BOOT);
}
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
diff --git a/src/soc/intel/common/acpi/platform.asl b/src/soc/intel/common/acpi/platform.asl
index 6a19792bf4..8afb6ff517 100644
--- a/src/soc/intel/common/acpi/platform.asl
+++ b/src/soc/intel/common/acpi/platform.asl
@@ -18,7 +18,7 @@ External(\_SB.PCI0.LPCB.EC0.WAK, MethodObj)
Method (_PTS, 1)
{
- DBG0 = POST_OS_ENTER_PTS
+ DBG0 = POSTCODE_OS_ENTER_PTS
If (CondRefOf (\_SB.PCI0.LPCB.EC0.PTS))
{
@@ -42,7 +42,7 @@ Method (_PTS, 1)
Method (_WAK, 1)
{
- DBG0 = POST_OS_ENTER_WAKE
+ DBG0 = POSTCODE_OS_ENTER_WAKE
If (CondRefOf (\_SB.PCI0.LPCB.EC0.WAK))
{
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index f2ae72c38a..5f6b6de07c 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -302,7 +302,7 @@ before_carstage:
/* Never reached */
.halt_forever:
- post_code(POST_DEAD_CODE)
+ post_code(POSTCODE_DEAD_CODE)
hlt
jmp .halt_forever
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
index 0126a122f6..7532c7d707 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
@@ -20,7 +20,7 @@ bootblock_pre_c_entry:
.global cache_as_ram
cache_as_ram:
- post_code(POST_BOOTBLOCK_CAR)
+ post_code(POSTCODE_BOOTBLOCK_CAR)
movl $(CONFIG_FSP_T_LOCATION), %ebx
add $0x94, %ebx
@@ -99,7 +99,7 @@ CAR_init_done:
/* Never reached */
.halt_forever:
- post_code(POST_DEAD_CODE)
+ post_code(POSTCODE_DEAD_CODE)
hlt
jmp .halt_forever
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index 81a5d342f0..f163e229a9 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -117,7 +117,7 @@ uintptr_t graphics_get_framebuffer_address(void)
memory_base = graphics_get_bar(dev, PCI_BASE_ADDRESS_2);
if (!memory_base)
- die_with_post_code(POST_HW_INIT_FAILURE,
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"Graphic memory bar2 is not programmed!");
memory_base += CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET;
@@ -140,7 +140,7 @@ static uintptr_t graphics_get_gtt_base(void)
if (!gtt_base) {
gtt_base = graphics_get_bar(dev, PCI_BASE_ADDRESS_0);
if (!gtt_base)
- die_with_post_code(POST_HW_INIT_FAILURE,
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"GTTMMADR is not programmed!");
}
return gtt_base;
diff --git a/src/soc/intel/common/block/p2sb/p2sblib.c b/src/soc/intel/common/block/p2sb/p2sblib.c
index 537f388cb2..70fbcaa147 100644
--- a/src/soc/intel/common/block/p2sb/p2sblib.c
+++ b/src/soc/intel/common/block/p2sb/p2sblib.c
@@ -50,7 +50,7 @@ void p2sb_dev_unhide(pci_devfn_t dev)
p2sb_dev_set_hide_bit(dev, 0);
if (p2sb_dev_is_hidden(dev))
- die_with_post_code(POST_HW_INIT_FAILURE,
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"Unable to unhide the P2SB device!\n");
}
@@ -59,7 +59,7 @@ void p2sb_dev_hide(pci_devfn_t dev)
p2sb_dev_set_hide_bit(dev, 1);
if (!p2sb_dev_is_hidden(dev))
- die_with_post_code(POST_HW_INIT_FAILURE,
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"Unable to hide the P2SB device!\n");
}
diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c
index 37d857978c..2805011a78 100644
--- a/src/soc/intel/common/block/pmc/pmc.c
+++ b/src/soc/intel/common/block/pmc/pmc.c
@@ -62,7 +62,7 @@ static void pch_pmc_read_resources(struct device *dev)
struct pmc_resource_config *config = &pmc_cfg;
if (pmc_soc_get_resources(config) < 0)
- die_with_post_code(POST_HW_INIT_FAILURE,
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"Unable to get PMC controller resource information!");
/* Get the normal PCI resources of this device. */
diff --git a/src/soc/intel/elkhartlake/finalize.c b/src/soc/intel/elkhartlake/finalize.c
index d6ab737de4..275413b4ef 100644
--- a/src/soc/intel/elkhartlake/finalize.c
+++ b/src/soc/intel/elkhartlake/finalize.c
@@ -49,7 +49,7 @@ static void soc_finalize(void *unused)
heci_finalize();
/* Indicate finalize step with post code */
- post_code(POST_OS_BOOT);
+ post_code(POSTCODE_OS_BOOT);
}
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c
index 5665d75340..6cff7a80f3 100644
--- a/src/soc/intel/jasperlake/finalize.c
+++ b/src/soc/intel/jasperlake/finalize.c
@@ -78,7 +78,7 @@ static void soc_finalize(void *unused)
apm_control(APM_CNT_FINALIZE);
/* Indicate finalize step with post code */
- post_code(POST_OS_BOOT);
+ post_code(POSTCODE_OS_BOOT);
}
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
diff --git a/src/soc/intel/meteorlake/chip.c b/src/soc/intel/meteorlake/chip.c
index d249dd4489..c2b1819f64 100644
--- a/src/soc/intel/meteorlake/chip.c
+++ b/src/soc/intel/meteorlake/chip.c
@@ -238,7 +238,7 @@ static void soc_init_final_device(void *chip_info)
fsp_handle_reset(reset_status);
/* Control shouldn't return here */
- die_with_post_code(POST_HW_INIT_FAILURE,
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"Failed to handle the FSP reset request with error 0x%08x\n", reset_status);
}
diff --git a/src/soc/intel/meteorlake/finalize.c b/src/soc/intel/meteorlake/finalize.c
index 6bd304cea6..a977b0516e 100644
--- a/src/soc/intel/meteorlake/finalize.c
+++ b/src/soc/intel/meteorlake/finalize.c
@@ -83,7 +83,7 @@ static void soc_finalize(void *unused)
heci_finalize();
/* Indicate finalize step with post code */
- post_code(POST_OS_BOOT);
+ post_code(POSTCODE_OS_BOOT);
}
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index afa1c02f4d..fd80aeac1a 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -109,7 +109,7 @@ static void soc_finalize(void *unused)
apm_control(APM_CNT_FINALIZE);
/* Indicate finalize step with post code */
- post_code(POST_OS_BOOT);
+ post_code(POSTCODE_OS_BOOT);
}
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c
index 283efb50df..cd02745a9e 100644
--- a/src/soc/intel/tigerlake/finalize.c
+++ b/src/soc/intel/tigerlake/finalize.c
@@ -61,7 +61,7 @@ static void soc_finalize(void *unused)
heci1_disable();
/* Indicate finalize step with post code */
- post_code(POST_OS_BOOT);
+ post_code(POSTCODE_OS_BOOT);
}
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
diff --git a/src/soc/intel/xeon_sp/finalize.c b/src/soc/intel/xeon_sp/finalize.c
index 7830a4b27f..af630fe812 100644
--- a/src/soc/intel/xeon_sp/finalize.c
+++ b/src/soc/intel/xeon_sp/finalize.c
@@ -70,7 +70,7 @@ static void soc_finalize(void *unused)
lock_msr_ppin_ctl(NULL);
}
- post_code(POST_OS_BOOT);
+ post_code(POSTCODE_OS_BOOT);
}
static void bios_done_finalize(void *unused)
diff --git a/src/southbridge/intel/common/finalize.c b/src/southbridge/intel/common/finalize.c
index 6fb27bbb4b..490bdae74e 100644
--- a/src/southbridge/intel/common/finalize.c
+++ b/src/southbridge/intel/common/finalize.c
@@ -50,5 +50,5 @@ void intel_pch_finalize_smm(void)
write_pmbase16(TCO1_CNT, read_pmbase16(TCO1_CNT) | TCO_LOCK);
- post_code(POST_OS_BOOT);
+ post_code(POSTCODE_OS_BOOT);
}
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index cacfbfb795..28cde3e45a 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -416,7 +416,7 @@ static void lpc_final(struct device *dev)
outw(tco1_cnt, DEFAULT_PMBASE + 0x60 + TCO1_CNT);
/* Indicate finalize step with post code */
- post_code(POST_OS_BOOT);
+ post_code(POSTCODE_OS_BOOT);
}
static const char *lpc_acpi_name(const struct device *dev)
diff --git a/src/vendorcode/google/chromeos/cr50_enable_update.c b/src/vendorcode/google/chromeos/cr50_enable_update.c
index 19f200605e..9fd8d99c7c 100644
--- a/src/vendorcode/google/chromeos/cr50_enable_update.c
+++ b/src/vendorcode/google/chromeos/cr50_enable_update.c
@@ -147,7 +147,7 @@ static void enable_update(void *unused)
mainboard_prepare_cr50_reset();
/* clear current post code avoid chatty eventlog on subsequent boot*/
- post_code(POST_CODE_CLEAR);
+ post_code(POSTCODE_CODE_CLEAR);
/*
* Older Cr50 firmware doesn't support the timeout parameter for the
diff --git a/util/cbfstool/eventlog.c b/util/cbfstool/eventlog.c
index 93590a1ee5..237360e109 100644
--- a/util/cbfstool/eventlog.c
+++ b/util/cbfstool/eventlog.c
@@ -369,59 +369,59 @@ static int eventlog_print_data(const struct event_header *event)
{0, NULL},
};
static const struct valstr coreboot_post_codes[] = {
- {POST_RESET_VECTOR_CORRECT, "Reset Vector Correct"},
- {POST_ENTER_PROTECTED_MODE, "Enter Protected Mode"},
- {POST_PREPARE_RAMSTAGE, "Prepare RAM stage"},
- {POST_ENTRY_C_START, "RAM stage Start"},
- {POST_MEM_PREINIT_PREP_START, "Preparing memory init params"},
- {POST_MEM_PREINIT_PREP_END, "Memory init param preparation complete"},
- {POST_CONSOLE_READY, "Console is ready"},
- {POST_CONSOLE_BOOT_MSG, "Console Boot Message"},
- {POST_ENABLING_CACHE, "Before Enabling Cache"},
- {POST_PRE_HARDWAREMAIN, "Before Hardware Main"},
- {POST_ENTRY_HARDWAREMAIN, "First call in Hardware Main"},
- {POST_BS_PRE_DEVICE, "Before Device Probe"},
- {POST_BS_DEV_INIT_CHIPS, "Initialize Chips"},
- {POST_BS_DEV_ENUMERATE, "Device Enumerate"},
- {POST_BS_DEV_RESOURCES, "Device Resource Allocation"},
- {POST_BS_DEV_ENABLE, "Device Enable"},
- {POST_BS_DEV_INIT, "Device Initialize"},
- {POST_BS_POST_DEVICE, "After Device Probe"},
- {POST_BS_OS_RESUME_CHECK, "OS Resume Check"},
- {POST_BS_OS_RESUME, "OS Resume"},
- {POST_BS_WRITE_TABLES, "Write Tables"},
- {POST_BS_PAYLOAD_LOAD, "Load Payload"},
- {POST_BS_PAYLOAD_BOOT, "Boot Payload"},
- {POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE, "FSP Notify Before End of Firmware"},
- {POST_FSP_NOTIFY_AFTER_END_OF_FIRMWARE, "FSP Notify After End of Firmware"},
- {POST_FSP_TEMP_RAM_INIT, "FSP-T Enter"},
- {POST_FSP_TEMP_RAM_EXIT, "FSP-T Exit"},
- {POST_FSP_MEMORY_INIT, "FSP-M Enter"},
- {POST_FSP_SILICON_INIT, "FSP-S Enter"},
- {POST_FSP_NOTIFY_BEFORE_ENUMERATE, "FSP Notify Before Enumerate"},
- {POST_FSP_NOTIFY_BEFORE_FINALIZE, "FSP Notify Before Finalize"},
- {POST_OS_ENTER_PTS, "ACPI _PTS Method"},
- {POST_OS_ENTER_WAKE, "ACPI _WAK Method"},
- {POST_FSP_MEMORY_EXIT, "FSP-M Exit"},
- {POST_FSP_SILICON_EXIT, "FSP-S Exit"},
- {POST_FSP_MULTI_PHASE_SI_INIT_ENTRY, "FSP-S Init Enter"},
- {POST_FSP_MULTI_PHASE_SI_INIT_EXIT, "FPS-S Init Exit"},
- {POST_FSP_NOTIFY_AFTER_ENUMERATE, "FSP Notify After Enumerate"},
- {POST_FSP_NOTIFY_AFTER_FINALIZE, "FSP Notify After Finalize"},
- {POST_INVALID_ROM, "Invalid ROM"},
- {POST_INVALID_CBFS, "Invalid CBFS"},
- {POST_INVALID_VENDOR_BINARY, "Invalid Vendor Binary"},
- {POST_RAM_FAILURE, "RAM Failure"},
- {POST_HW_INIT_FAILURE, "Hardware Init Failure"},
- {POST_VIDEO_FAILURE, "Video Failure"},
- {POST_TPM_FAILURE, "TPM Failure"},
- {POST_DEAD_CODE, "Dead Code"},
- {POST_RESUME_FAILURE, "Resume Failure"},
- {POST_JUMPING_TO_PAYLOAD, "Before Jump to Payload"},
- {POST_ENTER_ELF_BOOT, "Before ELF Boot"},
- {POST_OS_RESUME, "Before OS Resume"},
- {POST_OS_BOOT, "Before OS Boot"},
- {POST_DIE, "coreboot Dead"},
+ {POSTCODE_RESET_VECTOR_CORRECT, "Reset Vector Correct"},
+ {POSTCODE_ENTER_PROTECTED_MODE, "Enter Protected Mode"},
+ {POSTCODE_PREPARE_RAMSTAGE, "Prepare RAM stage"},
+ {POSTCODE_ENTRY_C_START, "RAM stage Start"},
+ {POSTCODE_MEM_PREINIT_PREP_START, "Preparing memory init params"},
+ {POSTCODE_MEM_PREINIT_PREP_END, "Memory init param preparation complete"},
+ {POSTCODE_CONSOLE_READY, "Console is ready"},
+ {POSTCODE_CONSOLE_BOOT_MSG, "Console Boot Message"},
+ {POSTCODE_ENABLING_CACHE, "Before Enabling Cache"},
+ {POSTCODE_PRE_HARDWAREMAIN, "Before Hardware Main"},
+ {POSTCODE_ENTRY_HARDWAREMAIN, "First call in Hardware Main"},
+ {POSTCODE_BS_PRE_DEVICE, "Before Device Probe"},
+ {POSTCODE_BS_DEV_INIT_CHIPS, "Initialize Chips"},
+ {POSTCODE_BS_DEV_ENUMERATE, "Device Enumerate"},
+ {POSTCODE_BS_DEV_RESOURCES, "Device Resource Allocation"},
+ {POSTCODE_BS_DEV_ENABLE, "Device Enable"},
+ {POSTCODE_BS_DEV_INIT, "Device Initialize"},
+ {POSTCODE_BS_POST_DEVICE, "After Device Probe"},
+ {POSTCODE_BS_OS_RESUME_CHECK, "OS Resume Check"},
+ {POSTCODE_BS_OS_RESUME, "OS Resume"},
+ {POSTCODE_BS_WRITE_TABLES, "Write Tables"},
+ {POSTCODE_BS_PAYLOAD_LOAD, "Load Payload"},
+ {POSTCODE_BS_PAYLOAD_BOOT, "Boot Payload"},
+ {POSTCODE_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE, "FSP Notify Before End of Firmware"},
+ {POSTCODE_FSP_NOTIFY_AFTER_END_OF_FIRMWARE, "FSP Notify After End of Firmware"},
+ {POSTCODE_FSP_TEMP_RAM_INIT, "FSP-T Enter"},
+ {POSTCODE_FSP_TEMP_RAM_EXIT, "FSP-T Exit"},
+ {POSTCODE_FSP_MEMORY_INIT, "FSP-M Enter"},
+ {POSTCODE_FSP_SILICON_INIT, "FSP-S Enter"},
+ {POSTCODE_FSP_NOTIFY_BEFORE_ENUMERATE, "FSP Notify Before Enumerate"},
+ {POSTCODE_FSP_NOTIFY_BEFORE_FINALIZE, "FSP Notify Before Finalize"},
+ {POSTCODE_OS_ENTER_PTS, "ACPI _PTS Method"},
+ {POSTCODE_OS_ENTER_WAKE, "ACPI _WAK Method"},
+ {POSTCODE_FSP_MEMORY_EXIT, "FSP-M Exit"},
+ {POSTCODE_FSP_SILICON_EXIT, "FSP-S Exit"},
+ {POSTCODE_FSP_MULTI_PHASE_SI_INIT_ENTRY, "FSP-S Init Enter"},
+ {POSTCODE_FSP_MULTI_PHASE_SI_INIT_EXIT, "FPS-S Init Exit"},
+ {POSTCODE_FSP_NOTIFY_AFTER_ENUMERATE, "FSP Notify After Enumerate"},
+ {POSTCODE_FSP_NOTIFY_AFTER_FINALIZE, "FSP Notify After Finalize"},
+ {POSTCODE_INVALID_ROM, "Invalid ROM"},
+ {POSTCODE_INVALID_CBFS, "Invalid CBFS"},
+ {POSTCODE_INVALID_VENDOR_BINARY, "Invalid Vendor Binary"},
+ {POSTCODE_RAM_FAILURE, "RAM Failure"},
+ {POSTCODE_HW_INIT_FAILURE, "Hardware Init Failure"},
+ {POSTCODE_VIDEO_FAILURE, "Video Failure"},
+ {POSTCODE_TPM_FAILURE, "TPM Failure"},
+ {POSTCODE_DEAD_CODE, "Dead Code"},
+ {POSTCODE_RESUME_FAILURE, "Resume Failure"},
+ {POSTCODE_JUMPING_TO_PAYLOAD, "Before Jump to Payload"},
+ {POSTCODE_ENTER_ELF_BOOT, "Before ELF Boot"},
+ {POSTCODE_OS_RESUME, "Before OS Resume"},
+ {POSTCODE_OS_BOOT, "Before OS Boot"},
+ {POSTCODE_DIE, "coreboot Dead"},
{0, NULL},
};
static const struct valstr mem_cache_slots[] = {