diff options
| -rw-r--r-- | src/soc/intel/common/block/gpio/gpio.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/common/block/pcr/pcr.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/Kconfig | 10 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/gpio.c | 129 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/include/soc/gpio.h | 52 |
6 files changed, 192 insertions, 2 deletions
diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index eea2554690..50a3a0266c 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -18,7 +18,6 @@ #include <gpio.h> #include <intelblocks/itss.h> #include <intelblocks/pcr.h> -#include <soc/pcr_ids.h> #include <soc/pm.h> #include <types.h> diff --git a/src/soc/intel/common/block/pcr/pcr.c b/src/soc/intel/common/block/pcr/pcr.c index 39f9bb832f..cf50fdc0aa 100644 --- a/src/soc/intel/common/block/pcr/pcr.c +++ b/src/soc/intel/common/block/pcr/pcr.c @@ -19,7 +19,6 @@ #include <intelblocks/pcr.h> #include <device/pci_ops.h> #include <soc/pci_devs.h> -#include <soc/pcr_ids.h> #include <timer.h> #if !defined(CONFIG_PCR_BASE_ADDRESS) || (CONFIG_PCR_BASE_ADDRESS == 0) diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 8d9a55002f..d666bcc88c 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -42,10 +42,14 @@ config CPU_SPECIFIC_OPTIONS select CACHE_MRC_SETTINGS select RELOCATABLE_RAMSTAGE # Build fails if this is not selected select PARALLEL_MP + select PCR_COMMON_IOSF_1_0 select SMP select SOC_INTEL_COMMON_BLOCK # select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_FAST_SPI + select SOC_INTEL_COMMON_BLOCK_GPIO + select DEBUG_SOC_COMMON_BLOCK_GPIO + select SOC_INTEL_COMMON_BLOCK_PCR select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE @@ -86,6 +90,12 @@ config MAX_CPUS int default 16 +config PCR_BASE_ADDRESS + hex + default 0xfd000000 + help + This option allows you to select MMIO Base Address of sideband bus. + config DCACHE_RAM_BASE hex default 0xfef00000 diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index 712b21c39e..3f6333dc0c 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -40,6 +40,7 @@ romstage-y += reset.c romstage-y += romstage.c romstage-y += tsc_freq.c romstage-y += gpio_dnv.c +romstage-y += gpio.c romstage-y += soc_util.c romstage-y += spi.c romstage-y += fiamux.c diff --git a/src/soc/intel/denverton_ns/gpio.c b/src/soc/intel/denverton_ns/gpio.c new file mode 100644 index 0000000000..30851fd75b --- /dev/null +++ b/src/soc/intel/denverton_ns/gpio.c @@ -0,0 +1,129 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 - 2017 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) + * Copyright (C) 2018 Online SAS + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <intelblocks/gpio.h> +#include <intelblocks/pcr.h> +#include <soc/pcr.h> +#include <soc/pm.h> + +static const struct reset_mapping rst_map[] = { + { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, + /* (applicable only for GPD group) */ + { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 }, +}; + +static const struct pad_group dnv_community_nc_groups[] = { + INTEL_GPP(NORTH_ALL_GBE0_SDP0, NORTH_ALL_GBE0_SDP0, NORTH_ALL_PCIE_CLKREQ3_N), + INTEL_GPP(NORTH_ALL_GBE0_SDP0, NORTH_ALL_PCIE_CLKREQ4_N, NORTH_ALL_MEMHOT_N), +}; + +static const struct pad_group dnv_community_sc_dfx_groups[] = { + INTEL_GPP(SOUTH_DFX_DFX_PORT_CLK0, SOUTH_DFX_DFX_PORT_CLK0, SOUTH_DFX_DFX_PORT15), +}; + +static const struct pad_group dnv_community_sc0_groups[] = { + INTEL_GPP(SOUTH_GROUP0_SMB3_CLTT_DATA, SOUTH_GROUP0_SMB3_CLTT_DATA, SOUTH_GROUP0_SATA0_LED_N), + INTEL_GPP(SOUTH_GROUP0_SMB3_CLTT_DATA, SOUTH_GROUP0_SATA1_LED_N, SOUTH_GROUP0_DFX_SPARE4), +}; + +static const struct pad_group dnv_community_sc1_groups[] = { + INTEL_GPP(SOUTH_GROUP1_SUSPWRDNACK, SOUTH_GROUP1_SUSPWRDNACK, SOUTH_GROUP1_EMMC_STROBE), + INTEL_GPP(SOUTH_GROUP1_SUSPWRDNACK, SOUTH_GROUP1_EMMC_CLK, SOUTH_GROUP1_GPIO_3), +}; + +static const struct pad_community dnv_gpio_communities[] = { + { + .port = PID_GPIOCOM1, + .first_pad = SOUTH_GROUP1_SUSPWRDNACK, + .last_pad = SOUTH_GROUP1_GPIO_3, + .num_gpi_regs = NUM_SC1_GPI_REGS, + .gpi_status_offset = NUM_NC_GPI_REGS + NUM_SC_DFX_GPI_REGS + + NUM_SC0_GPI_REGS, + .pad_cfg_base = R_PCH_PCR_GPIO_SC1_PADCFG_OFFSET, + .host_own_reg_0 = R_PCH_PCR_GPIO_SC1_PAD_OWN, + .gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_GPE_STS, + .gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_GPE_EN, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPIO_GPE_SC1", + .acpi_path = "\\_SB.GPO3", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = dnv_community_sc1_groups, + .num_groups = ARRAY_SIZE(dnv_community_sc1_groups), + }, { + .port = PID_GPIOCOM1, + .first_pad = SOUTH_GROUP0_SMB3_CLTT_DATA, + .last_pad = SOUTH_GROUP0_DFX_SPARE4, + .num_gpi_regs = NUM_SC0_GPI_REGS, + .gpi_status_offset = NUM_NC_GPI_REGS + NUM_SC_DFX_GPI_REGS, + .pad_cfg_base = R_PCH_PCR_GPIO_SC0_PADCFG_OFFSET, + .host_own_reg_0 = R_PCH_PCR_GPIO_SC0_PAD_OWN, + .gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_GPE_STS, + .gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_GPE_EN, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPIO_GPE_SC0", + .acpi_path = "\\_SB.GPO2", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = dnv_community_sc0_groups, + .num_groups = ARRAY_SIZE(dnv_community_sc0_groups), + }, { + .port = PID_GPIOCOM1, + .first_pad = SOUTH_DFX_DFX_PORT_CLK0, + .last_pad = SOUTH_DFX_DFX_PORT15, + .num_gpi_regs = NUM_SC_DFX_GPI_REGS, + .gpi_status_offset = NUM_NC_GPI_REGS, + .pad_cfg_base = R_PCH_PCR_GPIO_SC_DFX_PADCFG_OFFSET, + .host_own_reg_0 = R_PCH_PCR_GPIO_SC_DFX_HOSTSW_OWN, + .gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_SC_DFX_GPI_GPE_STS, + .gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_SC_DFX_GPI_GPE_EN, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPIO_GPE_SC_DFX", + .acpi_path = "\\_SB.GPO1", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = dnv_community_sc_dfx_groups, + .num_groups = ARRAY_SIZE(dnv_community_sc_dfx_groups), + }, { + .port = PID_GPIOCOM0, + .first_pad = NORTH_ALL_GBE0_SDP0, + .last_pad = NORTH_ALL_MEMHOT_N, + .num_gpi_regs = NUM_NC_GPI_REGS, + .gpi_status_offset = 0, + .pad_cfg_base = R_PCH_PCR_GPIO_NC_PADCFG_OFFSET, + .host_own_reg_0 = R_PCH_PCR_GPIO_NC_PAD_OWN, + .gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_NC_GPI_GPE_STS, + .gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_NC_GPI_GPE_EN, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPIO_GPE_NC", + .acpi_path = "\\_SB.GPO0", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = dnv_community_nc_groups, + .num_groups = ARRAY_SIZE(dnv_community_nc_groups), + } +}; + +const struct pad_community *soc_gpio_get_community(size_t *num_communities) +{ + *num_communities = ARRAY_SIZE(dnv_gpio_communities); + return dnv_gpio_communities; +} diff --git a/src/soc/intel/denverton_ns/include/soc/gpio.h b/src/soc/intel/denverton_ns/include/soc/gpio.h new file mode 100644 index 0000000000..082de218fd --- /dev/null +++ b/src/soc/intel/denverton_ns/include/soc/gpio.h @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Online SAS + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _SOC_DENVERTON_NS_GPIO_H_ +#define _SOC_DENVERTON_NS_GPIO_H_ + +#include <soc/gpio_defs.h> + +#define GPIO_MISCCFG 0x10 /* Miscellaneous Configuration offset */ + +#define GPIO_MAX_NUM_PER_GROUP 32 + + +#define NUM_NC_GPI_REGS \ + (ALIGN_UP(V_PCH_GPIO_NC_PAD_MAX, GPIO_MAX_NUM_PER_GROUP) \ + / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_SC_DFX_GPI_REGS \ + (ALIGN_UP(V_PCH_GPIO_SC_DFX_PAD_MAX, GPIO_MAX_NUM_PER_GROUP) \ + / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_SC0_GPI_REGS \ + (ALIGN_UP(V_PCH_GPIO_SC0_PAD_MAX, GPIO_MAX_NUM_PER_GROUP) \ + / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_SC1_GPI_REGS \ + (ALIGN_UP(V_PCH_GPIO_SC1_PAD_MAX, GPIO_MAX_NUM_PER_GROUP) \ + / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_GPI_STATUS_REGS (NUM_NC_GPI_REGS + NUM_SC_DFX_GPI_REGS +\ + NUM_SC0_GPI_REGS + NUM_SC1_GPI_REGS) + + +#define GPIO_NUM_PAD_CFG_REGS 2 /* DW0, DW1 */ + +#include <intelblocks/gpio.h>/* intelblocks/gpio.h depends on definitions in + lines above and soc/gpio_defs.h */ + +#endif /* _SOC_DENVERTON_NS_GPIO_H_ */ |