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-rw-r--r--src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb5
-rw-r--r--src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb5
2 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
index e71f15b8cf..a3c4c80d14 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
@@ -4,6 +4,11 @@ chip soc/intel/cannonlake
device lapic 0 on end
end
+ # FSP configuration
+ register "SaGv" = "3"
+ register "FspSkipMpInit" = "1"
+ register "SmbusEnable" = "1"
+
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
index e71f15b8cf..a3c4c80d14 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
@@ -4,6 +4,11 @@ chip soc/intel/cannonlake
device lapic 0 on end
end
+ # FSP configuration
+ register "SaGv" = "3"
+ register "FspSkipMpInit" = "1"
+ register "SmbusEnable" = "1"
+
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device