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-rw-r--r--src/soc/amd/cezanne/Kconfig5
-rw-r--r--src/soc/amd/cezanne/cpu.c3
2 files changed, 7 insertions, 1 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 82ab3c40c3..9e5209f50e 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -40,11 +40,14 @@ config SOC_SPECIFIC_OPTIONS
select SOC_AMD_COMMON_BLOCK_SPI
select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
select SOC_AMD_COMMON_BLOCK_UART
+ select SOC_AMD_COMMON_BLOCK_UCODE
select SSE2
- select SUPPORT_CPU_UCODE_IN_CBFS
select UDK_2017_BINDING
select X86_AMD_FIXED_MTRRS
+config SOC_AMD_COMMON_BLOCK_UCODE_SIZE
+ default 5568
+
config CHIPSET_DEVICETREE
string
default "soc/amd/cezanne/chipset.cb"
diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c
index b199d99251..2ec41a5196 100644
--- a/src/soc/amd/cezanne/cpu.c
+++ b/src/soc/amd/cezanne/cpu.c
@@ -2,6 +2,7 @@
#include <amdblocks/cpu.h>
#include <console/console.h>
+#include <cpu/amd/microcode.h>
#include <cpu/cpu.h>
#include <cpu/x86/lapic.h>
#include <device/device.h>
@@ -15,6 +16,8 @@ static void zen_2_3_init(struct device *dev)
{
setup_lapic();
set_cstate_io_addr();
+
+ amd_update_microcode_from_cbfs();
}
static struct device_operations cpu_dev_ops = {