diff options
| -rw-r--r-- | src/soc/intel/broadwell/lpc.c | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 6ebc758c46..9a4c65c8f3 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -49,6 +49,10 @@ #include <arch/acpigen.h> #include <cpu/cpu.h> +#if IS_ENABLED(CONFIG_CHROMEOS) +#include <vendorcode/google/chromeos/chromeos.h> +#endif + static void pch_enable_ioapic(struct device *dev) { u32 reg32; @@ -174,6 +178,25 @@ static void pch_power_options(device_t dev) enable_alt_smi(config->alt_gp_smi_en); } +#if IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS) +/* + * Preserve Vboot NV data when clearing CMOS as it will + * have been re-initialized already by Vboot firmware init. + */ +static void pch_cmos_init_preserve(int reset) +{ + uint8_t vbnv[CONFIG_VBNV_SIZE]; + + if (reset) + read_vbnv(vbnv); + + cmos_init(reset); + + if (reset) + save_vbnv(vbnv); +} +#endif + static void pch_rtc_init(struct device *dev) { u8 reg8; @@ -187,7 +210,11 @@ static void pch_rtc_init(struct device *dev) printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); } +#if IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS) + pch_cmos_init_preserve(rtc_failed); +#else cmos_init(rtc_failed); +#endif } static const struct reg_script pch_misc_init_script[] = { |