diff options
| -rw-r--r-- | src/soc/mediatek/common/dsi.c | 31 | ||||
| -rw-r--r-- | src/soc/mediatek/common/include/soc/dsi_common.h | 4 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/dsi.c | 30 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/include/soc/dsi.h | 5 |
4 files changed, 41 insertions, 29 deletions
diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index 92a645682e..12d536b497 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -37,6 +37,33 @@ static unsigned int mtk_dsi_get_bits_per_pixel(u32 format) return 24; } +static int mtk_dsi_get_data_rate(u32 bits_per_pixel, u32 lanes, + const struct edid *edid) +{ + /* data_rate = pixel_clock * bits_per_pixel * mipi_ratio / lanes + * Note pixel_clock comes in kHz and returned data_rate is in Mbps. + * mipi_ratio is the clk coefficient to balance the pixel clk in MIPI + * for older platforms which do not have complete implementation in HFP. + * Newer platforms should just set that to 1.0 (100 / 100). + */ + int data_rate = (u64)edid->mode.pixel_clock * bits_per_pixel * + MTK_DSI_MIPI_RATIO_NUMERATOR / + (1000 * lanes * MTK_DSI_MIPI_RATIO_DENOMINATOR); + printk(BIOS_INFO, "DSI data_rate: %d Mbps\n", data_rate); + + if (data_rate < MTK_DSI_DATA_RATE_MIN_MHZ) { + printk(BIOS_ERR, "data rate (%dMbps) must be >=%dMbps. " + "Please check the pixel clock (%u), bits per pixel(%u), " + "mipi_ratio (%d%%) and number of lanes (%d)\n", + data_rate, MTK_DSI_DATA_RATE_MIN_MHZ, + edid->mode.pixel_clock, bits_per_pixel, + (100 * MTK_DSI_MIPI_RATIO_NUMERATOR / + MTK_DSI_MIPI_RATIO_DENOMINATOR), lanes); + return -1; + } + return data_rate; +} + static void mtk_dsi_phy_timconfig(u32 data_rate) { u32 timcon0, timcon1, timcon2, timcon3; @@ -186,11 +213,11 @@ int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid) int data_rate; u32 bits_per_pixel = mtk_dsi_get_bits_per_pixel(format); - data_rate = mtk_dsi_phy_clk_setting(bits_per_pixel, lanes, edid); - + data_rate = mtk_dsi_get_data_rate(bits_per_pixel, lanes, edid); if (data_rate < 0) return -1; + mtk_dsi_configure_mipi_tx(data_rate, lanes); mtk_dsi_reset(); mtk_dsi_phy_timconfig(data_rate); mtk_dsi_rxtx_control(mode_flags, lanes); diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h index 7a48d53507..7241097380 100644 --- a/src/soc/mediatek/common/include/soc/dsi_common.h +++ b/src/soc/mediatek/common/include/soc/dsi_common.h @@ -302,9 +302,7 @@ enum { /* Functions that each SOC should provide. */ void mtk_dsi_reset(void); -/* mtk_dsi_phy_clk_setting should return the data rate in Mbps. */ -int mtk_dsi_phy_clk_setting(u32 bits_per_pixel, u32 lanes, - const struct edid *edid); +void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes); /* Public API provided in common/dsi.c */ int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, diff --git a/src/soc/mediatek/mt8173/dsi.c b/src/soc/mediatek/mt8173/dsi.c index 25030c621c..2e4a4bd58a 100644 --- a/src/soc/mediatek/mt8173/dsi.c +++ b/src/soc/mediatek/mt8173/dsi.c @@ -13,20 +13,19 @@ * GNU General Public License for more details. */ +#include <assert.h> #include <device/mmio.h> #include <console/console.h> #include <delay.h> -#include <edid.h> #include <soc/dsi.h> #include <timer.h> -int mtk_dsi_phy_clk_setting(u32 bits_per_pixel, u32 lanes, - const struct edid *edid) +void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes) { u32 txdiv0, txdiv1; u64 pcw; u32 reg; - int i, data_rate, mipi_tx_rate; + int i; reg = read32(&mipi_tx0->dsi_bg_con); @@ -52,16 +51,6 @@ int mtk_dsi_phy_clk_setting(u32 bits_per_pixel, u32 lanes, clrbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); - /** - * data_rate = pixel_clock / 1000 * bits_per_pixel * mipi_ratio / lanes - * pixel_clock unit is Khz, data_rata unit is MHz, so need divide 1000. - * mipi_ratio is mipi clk coefficient for balance the pixel clk in mipi. - * we set mipi_ratio is 1.02. - */ - data_rate = edid->mode.pixel_clock * 102 * bits_per_pixel / - (lanes * 1000 * 100); - mipi_tx_rate = data_rate; - if (data_rate > 500) { txdiv0 = 0; txdiv1 = 0; @@ -74,16 +63,11 @@ int mtk_dsi_phy_clk_setting(u32 bits_per_pixel, u32 lanes, } else if (data_rate >= 62) { txdiv0 = 2; txdiv1 = 1; - } else if (data_rate >= 50) { + } else { + /* MIN = 50 */ + assert(data_rate >= MTK_DSI_DATA_RATE_MIN_MHZ); txdiv0 = 2; txdiv1 = 2; - } else { - printk(BIOS_ERR, "data rate (%u) must be >=50. " - "Please check pixel clock (%u), bits per pixel (%u), " - "and number of lanes (%u)\n", - data_rate, edid->mode.pixel_clock, bits_per_pixel, - lanes); - return -1; } clrsetbits_le32(&mipi_tx0->dsi_pll_con0, @@ -115,8 +99,6 @@ int mtk_dsi_phy_clk_setting(u32 bits_per_pixel, u32 lanes, clrbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_SSC_EN); clrbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_PAD_TIE_LOW_EN); - - return mipi_tx_rate; } void mtk_dsi_reset(void) diff --git a/src/soc/mediatek/mt8173/include/soc/dsi.h b/src/soc/mediatek/mt8173/include/soc/dsi.h index f7c622745d..99c51e62ff 100644 --- a/src/soc/mediatek/mt8173/include/soc/dsi.h +++ b/src/soc/mediatek/mt8173/include/soc/dsi.h @@ -18,6 +18,11 @@ #include <soc/dsi_common.h> +/* DSI features */ +#define MTK_DSI_MIPI_RATIO_NUMERATOR 102 +#define MTK_DSI_MIPI_RATIO_DENOMINATOR 100 +#define MTK_DSI_DATA_RATE_MIN_MHZ 50 + /* MIPITX is SOC specific and cannot live in common. */ /* MIPITX_REG */ |