diff options
| -rw-r--r-- | src/superio/fintek/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/superio/fintek/f71808a/Kconfig | 18 | ||||
| -rw-r--r-- | src/superio/fintek/f71808a/Makefile.inc | 19 | ||||
| -rw-r--r-- | src/superio/fintek/f71808a/chip.h | 53 | ||||
| -rw-r--r-- | src/superio/fintek/f71808a/f71808a.h | 29 | ||||
| -rw-r--r-- | src/superio/fintek/f71808a/f71808a_hwm.c | 87 | ||||
| -rw-r--r-- | src/superio/fintek/f71808a/f71808a_multifunc.c | 57 | ||||
| -rw-r--r-- | src/superio/fintek/f71808a/fintek_internal.h | 27 | ||||
| -rw-r--r-- | src/superio/fintek/f71808a/superio.c | 74 |
9 files changed, 365 insertions, 0 deletions
diff --git a/src/superio/fintek/Makefile.inc b/src/superio/fintek/Makefile.inc index 0d0ae66738..2222644084 100644 --- a/src/superio/fintek/Makefile.inc +++ b/src/superio/fintek/Makefile.inc @@ -17,6 +17,7 @@ romstage-$(CONFIG_SUPERIO_FINTEK_COMMON_ROMSTAGE) += common/early_serial.c subdirs-y += f71805f +subdirs-y += f71808a subdirs-y += f71859 subdirs-y += f71863fg subdirs-y += f71869ad diff --git a/src/superio/fintek/f71808a/Kconfig b/src/superio/fintek/f71808a/Kconfig new file mode 100644 index 0000000000..756f28d22b --- /dev/null +++ b/src/superio/fintek/f71808a/Kconfig @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Nicola Corna <nicola@corna.info> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_FINTEK_F71808A + bool + select SUPERIO_FINTEK_COMMON_ROMSTAGE diff --git a/src/superio/fintek/f71808a/Makefile.inc b/src/superio/fintek/f71808a/Makefile.inc new file mode 100644 index 0000000000..f43e60245c --- /dev/null +++ b/src/superio/fintek/f71808a/Makefile.inc @@ -0,0 +1,19 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Nicola Corna <nicola@corna.info> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_FINTEK_F71808A) += f71808a_multifunc.c +ramstage-$(CONFIG_SUPERIO_FINTEK_F71808A) += f71808a_hwm.c +ramstage-$(CONFIG_SUPERIO_FINTEK_F71808A) += superio.c diff --git a/src/superio/fintek/f71808a/chip.h b/src/superio/fintek/f71808a/chip.h new file mode 100644 index 0000000000..f4e80ff839 --- /dev/null +++ b/src/superio/fintek/f71808a/chip.h @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com> + * Copyright (C) 2017 Nicola Corna <nicola@corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_FINTEK_F71808A_CHIP_H +#define SUPERIO_FINTEK_F71808A_CHIP_H + +#include <stdint.h> + +struct superio_fintek_f71808a_config { + + /* Multi function registers */ + uint8_t multi_function_register_0; + uint8_t multi_function_register_1; + uint8_t multi_function_register_2; + uint8_t multi_function_register_3; + uint8_t multi_function_register_4; + + /* Intel Ibex Peak/PECI/AMD TSI */ + uint8_t hwm_peci_tsi_ctrl; + uint8_t hwm_tcc_temp; + + /* Fan 1 control */ + uint8_t hwm_fan1_seg1_speed; + uint8_t hwm_fan1_seg2_speed; + uint8_t hwm_fan1_seg3_speed; + uint8_t hwm_fan1_seg4_speed; + uint8_t hwm_fan1_seg5_speed; + uint8_t hwm_fan1_temp_src; + + /* Fan 2 control */ + uint8_t hwm_fan2_seg1_speed; + uint8_t hwm_fan2_seg2_speed; + uint8_t hwm_fan2_seg3_speed; + uint8_t hwm_fan2_seg4_speed; + uint8_t hwm_fan2_seg5_speed; + uint8_t hwm_fan2_temp_src; +}; + +#endif /* SUPERIO_FINTEK_F71808A_CHIP_H */ diff --git a/src/superio/fintek/f71808a/f71808a.h b/src/superio/fintek/f71808a/f71808a.h new file mode 100644 index 0000000000..fbce494224 --- /dev/null +++ b/src/superio/fintek/f71808a/f71808a.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Nicola Corna <nicola@corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_FINTEK_F71808A_H +#define SUPERIO_FINTEK_F71808A_H + +/* Logical Device Numbers (LDN). */ +#define F71808A_SP1 0x01 /* UART1 */ +#define F71808A_HWM 0x04 /* Hardware monitor */ +#define F71808A_KBC 0x05 /* PS/2 keyboard and mouse */ +#define F71808A_GPIO 0x06 /* General Purpose I/O (GPIO) */ +#define F71808A_WDT 0x07 /* WDT */ +#define F71808A_CIR 0x08 /* CIR */ +#define F71808A_PME 0x0a /* Power Management Events (PME) and ACPI */ + +#endif /* SUPERIO_FINTEK_F71808A_H */ diff --git a/src/superio/fintek/f71808a/f71808a_hwm.c b/src/superio/fintek/f71808a/f71808a_hwm.c new file mode 100644 index 0000000000..1f533233a0 --- /dev/null +++ b/src/superio/fintek/f71808a/f71808a_hwm.c @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com> + * Copyright (C) 2017 Nicola Corna <nicola@corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pnp.h> +#include "fintek_internal.h" +#include "chip.h" + +/* Intel Ibex Peak/PECI/AMD TSI */ +#define HWM_PECI_TSI_CTRL_REG 0x0a +#define HWM_TCC_TEMPERATURE_REG 0x0c + +/* Fan 1 control */ +#define HWM_FAN1_SEG1_SPEED_REG 0xaa +#define HWM_FAN1_SEG2_SPEED_REG 0xab +#define HWM_FAN1_SEG3_SPEED_REG 0xac +#define HWM_FAN1_SEG4_SPEED_REG 0xad +#define HWM_FAN1_SEG5_SPEED_REG 0xae +#define HWM_FAN1_TEMP_SRC_REG 0xaf + +/* Fan 2 control */ +#define HWM_FAN2_SEG1_SPEED_REG 0xba +#define HWM_FAN2_SEG2_SPEED_REG 0xbb +#define HWM_FAN2_SEG3_SPEED_REG 0xbc +#define HWM_FAN2_SEG4_SPEED_REG 0xbd +#define HWM_FAN2_SEG5_SPEED_REG 0xbe +#define HWM_FAN2_TEMP_SRC_REG 0xbf + +void f71808a_hwm_init(struct device *dev) +{ + struct resource *res = find_resource(dev, PNP_IDX_IO0); + + if (!res) { + printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n"); + return; + } + + const struct superio_fintek_f71808a_config *reg = dev->chip_info; + u16 port = res->base; + + pnp_enter_conf_mode(dev); + + pnp_write_index(port, HWM_PECI_TSI_CTRL_REG, reg->hwm_peci_tsi_ctrl); + pnp_write_index(port, HWM_TCC_TEMPERATURE_REG, reg->hwm_tcc_temp); + + pnp_write_index(port, HWM_FAN1_SEG1_SPEED_REG, + reg->hwm_fan1_seg1_speed); + pnp_write_index(port, HWM_FAN1_SEG2_SPEED_REG, + reg->hwm_fan1_seg2_speed); + pnp_write_index(port, HWM_FAN1_SEG3_SPEED_REG, + reg->hwm_fan1_seg3_speed); + pnp_write_index(port, HWM_FAN1_SEG4_SPEED_REG, + reg->hwm_fan1_seg4_speed); + pnp_write_index(port, HWM_FAN1_SEG5_SPEED_REG, + reg->hwm_fan1_seg5_speed); + pnp_write_index(port, HWM_FAN1_TEMP_SRC_REG, reg->hwm_fan1_temp_src); + + pnp_write_index(port, HWM_FAN2_SEG1_SPEED_REG, + reg->hwm_fan2_seg1_speed); + pnp_write_index(port, HWM_FAN2_SEG2_SPEED_REG, + reg->hwm_fan2_seg2_speed); + pnp_write_index(port, HWM_FAN2_SEG3_SPEED_REG, + reg->hwm_fan2_seg3_speed); + pnp_write_index(port, HWM_FAN2_SEG4_SPEED_REG, + reg->hwm_fan2_seg4_speed); + pnp_write_index(port, HWM_FAN2_SEG5_SPEED_REG, + reg->hwm_fan2_seg5_speed); + pnp_write_index(port, HWM_FAN2_TEMP_SRC_REG, reg->hwm_fan2_temp_src); + + pnp_exit_conf_mode(dev); +} diff --git a/src/superio/fintek/f71808a/f71808a_multifunc.c b/src/superio/fintek/f71808a/f71808a_multifunc.c new file mode 100644 index 0000000000..be4ff04838 --- /dev/null +++ b/src/superio/fintek/f71808a/f71808a_multifunc.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com> + * Copyright (C) 2017 Nicola Corna <nicola@corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include "chip.h" +#include "fintek_internal.h" + +#define MULTI_FUNC_SEL_REG0 0x28 +#define MULTI_FUNC_SEL_REG1 0x29 +#define MULTI_FUNC_SEL_REG2 0x2A +#define MULTI_FUNC_SEL_REG3 0x2B +#define MULTI_FUNC_SEL_REG4 0x2C + +void f71808a_multifunc_init(struct device *dev) +{ + const struct superio_fintek_f71808a_config *conf = dev->chip_info; + + pnp_enter_conf_mode(dev); + + /* multi-func select reg0 */ + pnp_write_config(dev, MULTI_FUNC_SEL_REG0, + conf->multi_function_register_0); + + /* multi-func select reg1 */ + pnp_write_config(dev, MULTI_FUNC_SEL_REG1, + conf->multi_function_register_1); + + /* multi-func select reg2 */ + pnp_write_config(dev, MULTI_FUNC_SEL_REG2, + conf->multi_function_register_2); + + /* multi-func select reg3 */ + pnp_write_config(dev, MULTI_FUNC_SEL_REG3, + conf->multi_function_register_3); + + /* multi-func select reg4 */ + pnp_write_config(dev, MULTI_FUNC_SEL_REG4, + conf->multi_function_register_4); + + pnp_exit_conf_mode(dev); +} diff --git a/src/superio/fintek/f71808a/fintek_internal.h b/src/superio/fintek/f71808a/fintek_internal.h new file mode 100644 index 0000000000..715ae5d7b4 --- /dev/null +++ b/src/superio/fintek/f71808a/fintek_internal.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com> + * Copyright (C) 2017 Nicola Corna <nicola@corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_FINTEK_F71808A_INTERNAL_H +#define SUPERIO_FINTEK_F71808A_INTERNAL_H + +#include <arch/io.h> +#include <device/pnp.h> + +void f71808a_multifunc_init(struct device *dev); +void f71808a_hwm_init(struct device *dev); + +#endif /* SUPERIO_FINTEK_F71808A_INTERNAL_H */ diff --git a/src/superio/fintek/f71808a/superio.c b/src/superio/fintek/f71808a/superio.c new file mode 100644 index 0000000000..ee84dafcc0 --- /dev/null +++ b/src/superio/fintek/f71808a/superio.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com> + * Copyright (C) 2017 Nicola Corna <nicola@corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <console/console.h> +#include <stdlib.h> +#include <pc80/keyboard.h> + +#include "f71808a.h" +#include "fintek_internal.h" + +static void f71808a_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + /* TODO: Might potentially need code for UART, GPIO... */ + case F71808A_KBC: + pc_keyboard_init(NO_AUX_DEVICE); + break; + case F71808A_HWM: + f71808a_multifunc_init(dev); + f71808a_hwm_init(dev); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = f71808a_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + /* TODO: Some of the 0x07f8 etc. values may not be correct. */ + { &ops, F71808A_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F71808A_HWM, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F71808A_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, }, + { &ops, F71808A_GPIO, PNP_IRQ0, }, + { &ops, F71808A_WDT, PNP_IO0, {0x07f8, 0},}, + { &ops, F71808A_CIR, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F71808A_PME, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_fintek_f71808a_ops = { + CHIP_NAME("Fintek F71808A Super I/O") + .enable_dev = enable_dev +}; |