diff options
| -rw-r--r-- | src/mainboard/lenovo/t400/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x200/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/roda/rk9/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/gm45/northbridge.c | 15 |
4 files changed, 8 insertions, 13 deletions
diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 57f1f3753c..0bfdbc95aa 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -9,6 +9,7 @@ chip northbridge/intel/gm45 register "gpu_panel_power_cycle_delay" = "3" # T4: 200ms device cpu_cluster 0 on + ops gm45_cpu_bus_ops chip cpu/intel/socket_p device lapic 0 on end end @@ -28,6 +29,7 @@ chip northbridge/intel/gm45 register "pci_mmio_size" = "2048" device domain 0 on + ops gm45_pci_domain_ops device pci 00.0 on subsystemid 0x17aa 0x20e0 end # host bridge diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index 059dc005cb..dc059f0d50 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -9,6 +9,7 @@ chip northbridge/intel/gm45 register "gpu_panel_power_cycle_delay" = "3" # T4: 200ms device cpu_cluster 0 on + ops gm45_cpu_bus_ops chip cpu/intel/socket_BGA956 device lapic 0 on end end @@ -28,6 +29,7 @@ chip northbridge/intel/gm45 register "pci_mmio_size" = "2048" device domain 0 on + ops gm45_pci_domain_ops device pci 00.0 on subsystemid 0x17aa 0x20e0 end # host bridge diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb index c9c1896016..d4b4aef69a 100644 --- a/src/mainboard/roda/rk9/devicetree.cb +++ b/src/mainboard/roda/rk9/devicetree.cb @@ -2,6 +2,7 @@ chip northbridge/intel/gm45 # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" device cpu_cluster 0 on + ops gm45_cpu_bus_ops chip cpu/intel/socket_BGA956 device lapic 0 on end end @@ -21,6 +22,7 @@ chip northbridge/intel/gm45 register "pci_mmio_size" = "2048" device domain 0 on + ops gm45_pci_domain_ops subsystemid 0x4352 0x8986 device pci 00.0 on end # host bridge device pci 02.0 on end # VGA diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index df5526c244..31e3de46dc 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -200,7 +200,7 @@ static void pci_domain_ssdt(const struct device *dev) set_above_4g_pci(dev); } -static struct device_operations pci_domain_ops = { +struct device_operations gm45_pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, .init = mch_domain_init, @@ -210,22 +210,12 @@ static struct device_operations pci_domain_ops = { .acpi_name = northbridge_acpi_name, }; -static struct device_operations cpu_bus_ops = { +struct device_operations gm45_cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .init = mp_cpu_bus_init, }; -static void enable_dev(struct device *dev) -{ - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } -} - static void gm45_init(void *const chip_info) { int dev, fn, bit_base; @@ -265,6 +255,5 @@ static void gm45_init(void *const chip_info) struct chip_operations northbridge_intel_gm45_ops = { CHIP_NAME("Intel GM45 Northbridge") - .enable_dev = enable_dev, .init = gm45_init, }; |