diff options
17 files changed, 20 insertions, 57 deletions
diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb b/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb index 73f32e3a5d..0131e21948 100644 --- a/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb @@ -154,7 +154,6 @@ chip soc/intel/tigerlake end end device ref pcie_rp3 on - register "PcieRpEnable[2]" = "true" register "PcieRpLtrEnable[2]" = "true" register "PcieClkSrcUsage[1]" = "2" register "PcieClkSrcClkReq[1]" = "1" @@ -167,14 +166,12 @@ chip soc/intel/tigerlake device ref pcie_rp6 on # Card reader device pci 00.0 on end - register "PcieRpEnable[5]" = "true" register "PcieRpLtrEnable[5]" = "true" register "PcieClkSrcUsage[2]" = "5" register "PcieClkSrcClkReq[2]" = "2" end device ref pcie_rp9 on # SSD2 - PCIe mode - register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcClkReq[0]" = "0" diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 078deb29f2..fe13b77d5b 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -112,28 +112,24 @@ chip soc/intel/tigerlake # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" - # Enable NVMe PCIE 9 using clk 0 - register "PcieRpEnable[8]" = "1" + # NVMe PCIE 9 using clk 0 register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcClkReq[0]" = "0" register "PcieRpSlotImplemented[8]" = "1" - # Enable Optane PCIE 11 using clk 0 - register "PcieRpEnable[10]" = "1" + # Optane PCIE 11 using clk 0 register "PcieRpLtrEnable[10]" = "1" register "HybridStorageMode" = "0" register "PcieRpSlotImplemented[10]" = "1" - # Enable SD Card PCIE 8 using clk 3 - register "PcieRpEnable[7]" = "1" + # SD Card PCIE 8 using clk 3 register "PcieRpLtrEnable[7]" = "1" register "PcieRpHotPlug[7]" = "1" register "PcieClkSrcUsage[3]" = "7" register "PcieClkSrcClkReq[3]" = "3" - # Enable WLAN PCIE 7 using clk 1 - register "PcieRpEnable[6]" = "1" + # WLAN PCIE 7 using clk 1 register "PcieRpLtrEnable[6]" = "1" register "PcieClkSrcUsage[1]" = "6" register "PcieClkSrcClkReq[1]" = "1" @@ -469,7 +465,6 @@ chip soc/intel/tigerlake device ref i2c3 on end device ref heci1 on end device ref sata on end - device ref pcie_rp1 on end device ref pcie_rp7 on end device ref pcie_rp8 on probe DB_SD SD_GL9755S diff --git a/src/mainboard/google/volteer/variants/chronicler/overridetree.cb b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb index 28f72d70d6..53ed651bdd 100644 --- a/src/mainboard/google/volteer/variants/chronicler/overridetree.cb +++ b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb @@ -5,8 +5,7 @@ chip soc/intel/tigerlake register "DdiPort2Hpd" = "0" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}" - # Enable EMMC PCIE 5 using clk 5 - register "PcieRpEnable[4]" = "1" + # EMMC PCIE 5 using clk 5 register "PcieRpLtrEnable[4]" = "1" register "PcieRpHotPlug[4]" = "1" register "PcieClkSrcUsage[5]" = "4" diff --git a/src/mainboard/google/volteer/variants/elemi/overridetree.cb b/src/mainboard/google/volteer/variants/elemi/overridetree.cb index 2152ec479a..4adf76a882 100644 --- a/src/mainboard/google/volteer/variants/elemi/overridetree.cb +++ b/src/mainboard/google/volteer/variants/elemi/overridetree.cb @@ -5,8 +5,7 @@ chip soc/intel/tigerlake register "DdiPort2Hpd" = "0" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}" - # Enable EMMC PCIE 5 using clk 5 - register "PcieRpEnable[4]" = "1" + # EMMC PCIE 5 using clk 5 register "PcieRpLtrEnable[4]" = "1" register "PcieRpHotPlug[4]" = "1" register "PcieClkSrcUsage[5]" = "4" diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb index d101b5d34e..4c83c7e42d 100644 --- a/src/mainboard/google/volteer/variants/voema/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -12,13 +12,11 @@ chip soc/intel/tigerlake register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}" # Disable WLAN PCIE 7 - register "PcieRpEnable[6]" = "0" register "PcieRpLtrEnable[6]" = "0" register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" register "PcieRpSlotImplemented[6]" = "1" # Disable SD Card PCIE 8 - register "PcieRpEnable[7]" = "0" register "PcieRpLtrEnable[7]" = "0" register "PcieRpHotPlug[7]" = "0" register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" @@ -102,6 +100,16 @@ chip soc/intel/tigerlake probe AUDIO MAX98360_ALC5682I_I2S probe AUDIO RT1011_ALC5682I_I2S end + device ref pcie_rp7 off end + device ref pcie_rp8 off + # override-devicetree rules say it's only + # the same device if it has the same probes: + probe DB_SD SD_GL9755S + probe DB_SD SD_RTS5261 + probe DB_SD SD_RTS5227S + probe DB_SD SD_GL9750 + probe DB_SD SD_OZ711LV2LN + end device ref pcie_rp9 on chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 1af05c49cd..6a7db5f24d 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -37,10 +37,6 @@ chip soc/intel/tigerlake # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[10]" = "1" register "PcieRpSlotImplemented[2]" = "1" register "PcieRpSlotImplemented[3]" = "1" register "PcieRpSlotImplemented[8]" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index ad1a45d2e7..5960a3c752 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -38,10 +38,6 @@ chip soc/intel/tigerlake # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[10]" = "1" register "PcieRpSlotImplemented[2]" = "1" register "PcieRpSlotImplemented[3]" = "1" register "PcieRpSlotImplemented[8]" = "1" diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb index b870ec1410..2b7c4f8f8d 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb @@ -133,7 +133,6 @@ chip soc/intel/tigerlake device ref uart2 on end device ref pcie_rp9 on register "HybridStorageMode" = "0" - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[3]" = "0x08" register "PcieClkSrcClkReq[3]" = "3" diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb index d03bd2e432..ad90eabfee 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb @@ -53,21 +53,18 @@ chip soc/intel/tigerlake end device ref pcie_rp5 on # PCIe root port #5 x1, Clock 5 (GLAN) - register "PcieRpEnable[4]" = "1" register "PcieRpLtrEnable[4]" = "1" register "PcieClkSrcUsage[5]" = "4" register "PcieClkSrcClkReq[5]" = "5" end device ref pcie_rp7 on # PCIe root port #7 x1, Clock 7 (CARD) - register "PcieRpEnable[6]" = "1" register "PcieRpLtrEnable[6]" = "1" register "PcieClkSrcUsage[7]" = "6" register "PcieClkSrcClkReq[7]" = "7" end device ref pcie_rp8 on # PCIe root port #8 x1, Clock 8 (WLAN) - register "PcieRpEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[8]" = "7" register "PcieClkSrcClkReq[8]" = "8" @@ -75,7 +72,6 @@ chip soc/intel/tigerlake end device ref pcie_rp9 on # PCIe root port #9 x4, Clock 9 (SSD1) - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[9]" = "8" register "PcieClkSrcClkReq[9]" = "9" diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb index b463fe7b7b..bfbc5c5090 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb @@ -53,21 +53,18 @@ chip soc/intel/tigerlake end device ref pcie_rp5 on # PCIe root port #5 x1, Clock 8 (GLAN) - register "PcieRpEnable[4]" = "1" register "PcieRpLtrEnable[4]" = "1" #register "PcieClkSrcUsage[8]" = "4" register "PcieClkSrcClkReq[8]" = "8" end device ref pcie_rp7 on # PCIe root port #7 x1, Clock 3 (CARD) - register "PcieRpEnable[6]" = "1" register "PcieRpLtrEnable[6]" = "1" register "PcieClkSrcUsage[3]" = "6" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp8 on # PCIe root port #8 x1, Clock 2 (WLAN) - register "PcieRpEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[2]" = "7" register "PcieClkSrcClkReq[2]" = "2" @@ -75,7 +72,6 @@ chip soc/intel/tigerlake end device ref pcie_rp9 on # PCIe root port #9 x4, Clock 10 (SSD2) - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[10]" = "8" register "PcieClkSrcClkReq[10]" = "10" diff --git a/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb b/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb index 6f25d7bb7c..a09cf30cad 100644 --- a/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb +++ b/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb @@ -62,21 +62,18 @@ chip soc/intel/tigerlake end device ref pcie_rp5 on # PCIe root port #5 x1, Clock 8 (GLAN) - register "PcieRpEnable[4]" = "1" register "PcieRpLtrEnable[4]" = "1" register "PcieClkSrcUsage[8]" = "4" register "PcieClkSrcClkReq[8]" = "8" end device ref pcie_rp6 on # PCIe root port #6 x1, Clock 10 (CARD) - register "PcieRpEnable[5]" = "1" register "PcieRpLtrEnable[5]" = "1" register "PcieClkSrcUsage[10]" = "5" register "PcieClkSrcClkReq[10]" = "10" end device ref pcie_rp8 on # PCIe root port #8 x1, Clock 2 (WLAN) - register "PcieRpEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[2]" = "7" register "PcieClkSrcClkReq[2]" = "2" @@ -84,7 +81,6 @@ chip soc/intel/tigerlake end device ref pcie_rp9 on # PCIe root port #9 x4, Clock 6 (SSD2) - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[6]" = "8" register "PcieClkSrcClkReq[6]" = "6" diff --git a/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb b/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb index 9a669ef7fd..a35dc52ab9 100644 --- a/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb +++ b/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb @@ -141,14 +141,12 @@ chip soc/intel/tigerlake end device ref pcie_rp6 on # PCIe root port #6 x1, Clock 2 (CARD) - register "PcieRpEnable[5]" = "1" register "PcieRpLtrEnable[5]" = "1" register "PcieClkSrcUsage[2]" = "5" register "PcieClkSrcClkReq[2]" = "2" end device ref pcie_rp7 on # PCIe root port #7 x1, Clock 3 (GLAN) - register "PcieRpEnable[6]" = "1" register "PcieRpLtrEnable[6]" = "1" register "PcieClkSrcUsage[3]" = "6" register "PcieClkSrcClkReq[3]" = "3" @@ -161,7 +159,6 @@ chip soc/intel/tigerlake end device ref pcie_rp8 on # PCIe root port #8 x1, Clock 1 (WLAN) - register "PcieRpEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[1]" = "7" register "PcieClkSrcClkReq[1]" = "1" @@ -169,7 +166,6 @@ chip soc/intel/tigerlake end device ref pcie_rp9 on # PCIe root port #9 x4, Clock 4 (SSD0) - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[4]" = "8" register "PcieClkSrcClkReq[4]" = "4" diff --git a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb index 7c3475e466..075a2e44ab 100644 --- a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb +++ b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb @@ -141,7 +141,6 @@ chip soc/intel/tigerlake end device ref pcie_rp5 on # PCIe root port #5 x4, Clock 2 (NVIDIA GPU) - register "PcieRpEnable[4]" = "1" register "PcieRpLtrEnable[4]" = "1" register "PcieClkSrcUsage[2]" = "4" register "PcieClkSrcClkReq[2]" = "2" @@ -158,14 +157,12 @@ chip soc/intel/tigerlake end device ref pcie_rp9 on # PCIe root port #9 x1, Clock 3 (CARD) - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[3]" = "8" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp10 on # PCIe root port #10 x1, Clock 4 (GLAN) - register "PcieRpEnable[9]" = "1" register "PcieRpLtrEnable[9]" = "1" register "PcieClkSrcUsage[4]" = "9" register "PcieClkSrcClkReq[4]" = "4" @@ -178,7 +175,6 @@ chip soc/intel/tigerlake end device ref pcie_rp11 on # PCIe root port #11 x1, Clock 1 (WLAN) - register "PcieRpEnable[10]" = "1" register "PcieRpLtrEnable[10]" = "1" register "PcieClkSrcUsage[1]" = "10" register "PcieClkSrcClkReq[1]" = "1" diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb b/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb index 671cdc4a54..ce4507900e 100644 --- a/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb +++ b/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb @@ -118,7 +118,6 @@ chip soc/intel/tigerlake end device ref pcie_rp3 on # PCIe root port #3 x1, Clock 1 (WLAN) - register "PcieRpEnable[2]" = "1" register "PcieRpLtrEnable[2]" = "1" register "PcieClkSrcUsage[1]" = "2" register "PcieClkSrcClkReq[1]" = "1" @@ -126,7 +125,6 @@ chip soc/intel/tigerlake end device ref pcie_rp6 on # PCIe root port #6 x1, Clock 2 (CARD) - register "PcieRpEnable[5]" = "1" register "PcieRpLtrEnable[5]" = "1" register "PcieClkSrcUsage[2]" = "5" register "PcieClkSrcClkReq[2]" = "2" @@ -134,7 +132,6 @@ chip soc/intel/tigerlake device ref pcie_rp9 on # PCIe root port #9 x4, Clock 0 (SSD2) # Despite the name, SSD1_CLKREQ# is used for SSD2 - register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcClkReq[0]" = "0" diff --git a/src/soc/intel/tigerlake/Makefile.mk b/src/soc/intel/tigerlake/Makefile.mk index 435572e10a..27e07a99b4 100644 --- a/src/soc/intel/tigerlake/Makefile.mk +++ b/src/soc/intel/tigerlake/Makefile.mk @@ -20,6 +20,7 @@ bootblock-y += p2sb.c romstage-y += espi.c romstage-y += meminit.c +romstage-y += pcie_rp.c romstage-y += reset.c ramstage-y += acpi.c diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 3de8ffaf43..8700dd5d51 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -258,7 +258,6 @@ struct soc_intel_tigerlake_config { uint8_t PchHdaIDispCodecDisconnect; /* PCIe Root Ports */ - uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; /* Implemented as slot or built-in? */ uint8_t PcieRpSlotImplemented[CONFIG_MAX_ROOT_PORTS]; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index afcbf2f711..baf2eb36cf 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -9,6 +9,7 @@ #include <fsp/util.h> #include <gpio.h> #include <intelblocks/cpulib.h> +#include <intelblocks/pcie_rp.h> #include <option.h> #include <soc/iomap.h> #include <soc/msr.h> @@ -21,7 +22,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_tigerlake_config *config) { unsigned int i; - uint32_t cpu_id, mask = 0; + uint32_t cpu_id; m_cfg->HyperThreading = get_uint_option("hyper_threading", CONFIG(FSP_HYPERTHREADING)); @@ -49,11 +50,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; } - for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { - if (config->PcieRpEnable[i]) - mask |= (1 << i); - } - m_cfg->PcieRpEnableMask = mask; + m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(soc_get_pch_rp_groups()); memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage, sizeof(config->PcieClkSrcUsage)); |