14 files changed, 30 insertions, 8 deletions

diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c
index bd9f06cdec..25cf5b37c2 100644
--- a/src/mainboard/amd/gardenia/mainboard.c
+++ b/src/mainboard/amd/gardenia/mainboard.c
@@ -17,7 +17,7 @@
 #include <device/device.h>
 #include <arch/acpi.h>
 #include <agesawrapper.h>
-#include <amd_pci_util.h>
+#include <amdblocks/amd_pci_util.h>
 
 /***********************************************************
  * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
diff --git a/src/mainboard/amd/gardenia/mptable.c b/src/mainboard/amd/gardenia/mptable.c
index 5c07186327..e29b3e3703 100644
--- a/src/mainboard/amd/gardenia/mptable.c
+++ b/src/mainboard/amd/gardenia/mptable.c
@@ -23,7 +23,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <soc/southbridge.h>
-#include <amd_pci_util.h>
+#include <amdblocks/amd_pci_util.h>
 
 static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
 {
diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c
index 8e0358a997..fc13567aae 100644
--- a/src/mainboard/google/kahlee/mainboard.c
+++ b/src/mainboard/google/kahlee/mainboard.c
@@ -17,7 +17,7 @@
 #include <device/device.h>
 #include <arch/acpi.h>
 #include <agesawrapper.h>
-#include <amd_pci_util.h>
+#include <amdblocks/amd_pci_util.h>
 #include <cbmem.h>
 #include <baseboard/variants.h>
 #include <boardid.h>
diff --git a/src/mainboard/google/kahlee/mptable.c b/src/mainboard/google/kahlee/mptable.c
index 5c07186327..e29b3e3703 100644
--- a/src/mainboard/google/kahlee/mptable.c
+++ b/src/mainboard/google/kahlee/mptable.c
@@ -23,7 +23,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <soc/southbridge.h>
-#include <amd_pci_util.h>
+#include <amdblocks/amd_pci_util.h>
 
 static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
 {
diff --git a/src/soc/amd/common/Makefile.inc b/src/soc/amd/common/Makefile.inc
index 22eb0d6f74..b485bb3479 100644
--- a/src/soc/amd/common/Makefile.inc
+++ b/src/soc/amd/common/Makefile.inc
@@ -12,10 +12,9 @@ romstage-y += heapmanager.c
 
 ramstage-y += agesawrapper.c
 ramstage-y += amd_late_init.c
-ramstage-y += amd_pci_util.c
 ramstage-y += def_callouts.c
 ramstage-y += heapmanager.c
-ramstage-$(CONFIG_SPI_FLASH) += spi.c
+
 subdirs-$(CONFIG_SOC_AMD_COMMON_BLOCK) += block
 
 endif
diff --git a/src/soc/amd/common/amd_pci_util.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h
index 92d27dcca7..92d27dcca7 100644
--- a/src/soc/amd/common/amd_pci_util.h
+++ b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h
diff --git a/src/soc/amd/common/block/pci/Kconfig b/src/soc/amd/common/block/pci/Kconfig
new file mode 100644
index 0000000000..74ea69784d
--- /dev/null
+++ b/src/soc/amd/common/block/pci/Kconfig
@@ -0,0 +1,6 @@
+config SOC_AMD_COMMON_BLOCK_PCI
+	bool
+	default n
+	help
+	  This option builds functions used to program PCI interrupt
+	  routing, both PIC and APIC modes.
diff --git a/src/soc/amd/common/block/pci/Makefile.inc b/src/soc/amd/common/block/pci/Makefile.inc
new file mode 100644
index 0000000000..fc40c9d478
--- /dev/null
+++ b/src/soc/amd/common/block/pci/Makefile.inc
@@ -0,0 +1,5 @@
+ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PCI),y)
+
+ramstage-y += amd_pci_util.c
+
+endif
diff --git a/src/soc/amd/common/amd_pci_util.c b/src/soc/amd/common/block/pci/amd_pci_util.c
index ca022fbdbb..d30adf4134 100644
--- a/src/soc/amd/common/amd_pci_util.c
+++ b/src/soc/amd/common/block/pci/amd_pci_util.c
@@ -18,7 +18,7 @@
 #include <device/pci.h>
 #include <arch/io.h>
 #include <string.h>
-#include <amd_pci_util.h>
+#include <amdblocks/amd_pci_util.h>
 #include <pc80/i8259.h>
 #include <soc/amd_pci_int_defs.h>
 
diff --git a/src/soc/amd/common/block/s3/Kconfig b/src/soc/amd/common/block/s3/Kconfig
new file mode 100644
index 0000000000..85863ca42f
--- /dev/null
+++ b/src/soc/amd/common/block/s3/Kconfig
@@ -0,0 +1,5 @@
+config SOC_AMD_COMMON_BLOCK_S3
+	bool
+	default n
+	help
+	  Select this option to add S3 related functions to the build.
diff --git a/src/soc/amd/common/block/s3/Makefile.inc b/src/soc/amd/common/block/s3/Makefile.inc
new file mode 100644
index 0000000000..f19cb2e3b4
--- /dev/null
+++ b/src/soc/amd/common/block/s3/Makefile.inc
@@ -0,0 +1,5 @@
+ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_S3),y)
+
+ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c
+
+endif
diff --git a/src/soc/amd/common/spi.c b/src/soc/amd/common/block/s3/spi.c
index f72416ad97..f72416ad97 100644
--- a/src/soc/amd/common/spi.c
+++ b/src/soc/amd/common/block/s3/spi.c
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index dd95b85677..8b9111e81e 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -46,8 +46,10 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_AMD_PI
 	select SOC_AMD_COMMON
 	select SOC_AMD_COMMON_BLOCK
+	select SOC_AMD_COMMON_BLOCK_PCI
 	select SOC_AMD_COMMON_BLOCK_PSP
 	select SOC_AMD_COMMON_BLOCK_CAR
+	select SOC_AMD_COMMON_BLOCK_S3
 	select C_ENVIRONMENT_BOOTBLOCK
 	select BOOTBLOCK_CONSOLE
 	select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index f8e06b3c5e..ed1d10a591 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -24,7 +24,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <cbmem.h>
-#include <amd_pci_util.h>
+#include <amdblocks/amd_pci_util.h>
 #include <soc/southbridge.h>
 #include <soc/smi.h>
 #include <soc/amd_pci_int_defs.h>