diff options
| -rw-r--r-- | src/soc/intel/skylake/bootblock/pch.c | 23 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/iomap.h | 2 |
2 files changed, 25 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 22ab1090b8..57b5fedb24 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -251,6 +251,27 @@ static void soc_config_rtc(void) B_PCH_PCR_RTC_CONF_UCMOS_EN); } +static void enable_heci(void) +{ + device_t dev = PCH_DEV_ME; + u8 pcireg; + + /* Assign Resources to HECI1 */ + /* Clear BIT 1-2 of Command Register */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config8(dev, PCI_COMMAND, pcireg); + + /* Program Temporary BAR for HECI1 */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, HECI1_BASE_ADDRESS); + pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0); + + /* Enable Bus Master and MMIO Space */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config8(dev, PCI_COMMAND, pcireg); +} + void pch_early_init(void) { /* @@ -281,4 +302,6 @@ void pch_early_init(void) enable_smbus(); soc_config_rtc(); + + enable_heci(); } diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index feba3027e7..e736d3b514 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -56,6 +56,8 @@ #define GPIO_BASE_SIZE 0x10000 +#define HECI1_BASE_ADDRESS 0xfed1a000 + /* * I/O port address space */ |