diff options
| -rw-r--r-- | src/drivers/intel/fsp2_0/Kconfig | 16 | ||||
| -rw-r--r-- | src/drivers/intel/fsp2_0/include/fsp/api.h | 4 | ||||
| -rw-r--r-- | src/drivers/intel/fsp2_0/silicon_init.c | 24 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 8 | ||||
| -rw-r--r-- | src/soc/intel/common/block/tcss/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/jasperlake/fsp_params.c | 6 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/ramstage.c | 6 |
9 files changed, 40 insertions, 30 deletions
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 3b03b6d1b7..ba93baa4de 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -274,4 +274,20 @@ config SOC_INTEL_COMMON_FSP_RESET Common code block to handle platform reset request raised by FSP. The FSP will use the FSP EAS v2.0 section 12.2.2 (OEM Status Code) to indicate that a reset is required. + +config FSPS_HAS_ARCH_UPD + bool + help + SoC users must select this Kconfig if the `FSPS_UPD` header has architecture + UPD structure as `FSPS_ARCH_UPD`. Typically, platform with FSP 2.2 specification + onwards has support for `FSPS_ARCH_UPD` section as part of `FSPS_UPD` structure. + But there are some exceptions as in TGL, JSL, XEON_SP FSP header doesn't have + support for FSPS_ARCH_UPD. + +config FSPS_USE_MULTI_PHASE_INIT + bool + help + SoC users to select this Kconfig to set EnableMultiPhaseSiliconInit to enable and + execute FspMultiPhaseSiInit() API. + endif diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index a095b78b5f..68b84703ca 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -47,8 +47,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version); void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd); /* Callbacks for SoC/Mainboard specific overrides */ void platform_fsp_multi_phase_init_cb(uint32_t phase_index); -/* Check if SoC sets EnableMultiPhaseSiliconInit UPD */ -int soc_fsp_multi_phase_init_is_enable(void); +/* Check if MultiPhase Si Init is enabled */ +bool fsp_is_multi_phase_init_enabled(void); /* * The following functions are used when FSP_PLATFORM_MEMORY_SETTINGS_VERSION * is employed allowing the mainboard and SoC to supply their own version diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index bf5230e90d..b3e60c25c3 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -29,11 +29,6 @@ void __weak platform_fsp_multi_phase_init_cb(uint32_t phase_index) /* Leave for the SoC/Mainboard to implement if necessary. */ } -int __weak soc_fsp_multi_phase_init_is_enable(void) -{ - return 1; -} - /* FSP Specification < 2.2 has only 1 stage like FspSiliconInit. FSP specification >= 2.2 * has multiple stages as below. */ @@ -77,6 +72,20 @@ static void fsps_return_value_handler(enum fsp_silicon_init_phases phases, uint3 } } +bool fsp_is_multi_phase_init_enabled(void) +{ + return CONFIG(FSPS_USE_MULTI_PHASE_INIT) && + (fsps_hdr.multi_phase_si_init_entry_offset != 0); +} + +static void fsp_fill_common_arch_params(FSPS_UPD *supd) +{ +#if CONFIG(FSPS_HAS_ARCH_UPD) + FSPS_ARCH_UPD *s_arch_cfg = &supd->FspsArchUpd; + s_arch_cfg->EnableMultiPhaseSiliconInit = fsp_is_multi_phase_init_enabled(); +#endif +} + static void do_silicon_init(struct fsp_header *hdr) { FSPS_UPD *upd, *supd; @@ -106,6 +115,9 @@ static void do_silicon_init(struct fsp_header *hdr) memcpy(upd, supd, hdr->cfg_region_size); + /* Fill common settings on behalf of chipset. */ + if (CONFIG(FSPS_HAS_ARCH_UPD)) + fsp_fill_common_arch_params(upd); /* Give SoC/mainboard a chance to populate entries */ platform_fsp_silicon_init_params_cb(upd); @@ -145,7 +157,7 @@ static void do_silicon_init(struct fsp_header *hdr) return; /* Check if SoC user would like to call Multi Phase Init */ - if (!soc_fsp_multi_phase_init_is_enable()) + if (!fsp_is_multi_phase_init_enabled()) return; /* Call MultiPhaseSiInit */ diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 0b28938401..915dd3f381 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -24,6 +24,7 @@ config CPU_SPECIFIC_OPTIONS select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW select FSP_M_XIP select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 + select FSPS_HAS_ARCH_UPD select GENERIC_GPIO_LIB select HAVE_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 107d22e9e4..541a9612d8 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -672,12 +672,6 @@ static void fill_fsps_fivr_params(FSP_S_CONFIG *s_cfg, config->ext_fivr_settings.vnn_icc_max_ma; } -static void arch_silicon_init_params(FSPS_ARCH_UPD *s_arch_cfg) -{ - /* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */ - s_arch_cfg->EnableMultiPhaseSiliconInit = 1; -} - static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, struct soc_intel_alderlake_config *config) { @@ -718,10 +712,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { struct soc_intel_alderlake_config *config; FSP_S_CONFIG *s_cfg = &supd->FspsConfig; - FSPS_ARCH_UPD *s_arch_cfg = &supd->FspsArchUpd; config = config_of_soc(); - arch_silicon_init_params(s_arch_cfg); soc_silicon_init_params(s_cfg, config); mainboard_silicon_init_params(s_cfg); } diff --git a/src/soc/intel/common/block/tcss/Kconfig b/src/soc/intel/common/block/tcss/Kconfig index 3eb0931611..2e679138cd 100644 --- a/src/soc/intel/common/block/tcss/Kconfig +++ b/src/soc/intel/common/block/tcss/Kconfig @@ -1,5 +1,6 @@ config SOC_INTEL_COMMON_BLOCK_TCSS def_bool n + select FSPS_USE_MULTI_PHASE_INIT help Sets up USB2/3 port mapping in TCSS MUX and sets MUX to disconnect state diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 11b146b577..18db9359ce 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -204,12 +204,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) mainboard_silicon_init_params(params); } -/* Disable Multiphase Si init */ -int soc_fsp_multi_phase_init_is_enable(void) -{ - return 0; -} - /* Mainboard GPIO Configuration */ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) { diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index bb100df633..892363b75c 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -565,8 +565,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) config->PchPmSlpS3MinAssert, config->PchPmSlpAMinAssert, config->PchPmPwrCycDur); - /* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */ - params->EnableMultiPhaseSiliconInit = 1; + /* Override EnableMultiPhaseSiliconInit prior calling MultiPhaseSiInit */ + params->EnableMultiPhaseSiliconInit = fsp_is_multi_phase_init_enabled(); /* Disable C1 C-state Demotion */ params->C1StateAutoDemotion = 0; diff --git a/src/soc/intel/xeon_sp/cpx/ramstage.c b/src/soc/intel/xeon_sp/cpx/ramstage.c index 1e0ba008c2..cd1b038b52 100644 --- a/src/soc/intel/xeon_sp/cpx/ramstage.c +++ b/src/soc/intel/xeon_sp/cpx/ramstage.c @@ -1,13 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <fsp/api.h> #include <smbios.h> -int soc_fsp_multi_phase_init_is_enable(void) -{ - return 0; -} - unsigned int smbios_cpu_get_max_speed_mhz(void) { return 3900; |