diff options
| -rw-r--r-- | src/soc/amd/common/block/acpimmio/mmio_util.c | 15 | ||||
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/acpimmio.h | 3 | ||||
| -rw-r--r-- | src/soc/amd/picasso/psp_verstage/fch.c | 5 | ||||
| -rw-r--r-- | src/soc/amd/picasso/psp_verstage/psp_verstage.c | 3 | ||||
| -rw-r--r-- | src/soc/amd/picasso/psp_verstage/psp_verstage.h | 1 | ||||
| -rw-r--r-- | src/soc/amd/picasso/southbridge.c | 18 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 18 |
7 files changed, 24 insertions, 39 deletions
diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index 508467297c..6231d49e12 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -58,6 +58,21 @@ void enable_acpimmio_decode_pm04(void) pm_io_write32(ACPIMMIO_DECODE_REGISTER_04, dw); } +void fch_enable_cf9_io(void) +{ + pm_write32(PM_DECODE_EN, pm_read32(PM_DECODE_EN) | CF9_IO_EN); +} + +void fch_enable_legacy_io(void) +{ + pm_write32(PM_DECODE_EN, pm_read32(PM_DECODE_EN) | LEGACY_IO_EN); +} + +void fch_io_enable_legacy_io(void) +{ + pm_io_write32(PM_DECODE_EN, pm_io_read32(PM_DECODE_EN) | LEGACY_IO_EN); +} + /* PM registers are accessed a byte at a time via CD6/CD7 */ uint8_t pm_io_read8(uint8_t reg) { diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 865ad48a9b..0e42ee60c3 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -73,6 +73,9 @@ void enable_acpimmio_decode_pm24(void); /* For newer integrated FCHs */ void enable_acpimmio_decode_pm04(void); +void fch_enable_cf9_io(void); +void fch_enable_legacy_io(void); +void fch_io_enable_legacy_io(void); /* Access PM registers using IO cycles */ uint8_t pm_io_read8(uint8_t reg); diff --git a/src/soc/amd/picasso/psp_verstage/fch.c b/src/soc/amd/picasso/psp_verstage/fch.c index b813770b4a..e6c70f62ee 100644 --- a/src/soc/amd/picasso/psp_verstage/fch.c +++ b/src/soc/amd/picasso/psp_verstage/fch.c @@ -102,11 +102,6 @@ uintptr_t *map_spi_rom(void) return addr; } -void sb_enable_legacy_io(void) -{ - pm_io_write32(PM_DECODE_EN, pm_io_read32(PM_DECODE_EN) | LEGACY_IO_EN); -} - static uint32_t map_fch_devices(void) { void *bar; diff --git a/src/soc/amd/picasso/psp_verstage/psp_verstage.c b/src/soc/amd/picasso/psp_verstage/psp_verstage.c index f367dce6fd..8ef2dcde34 100644 --- a/src/soc/amd/picasso/psp_verstage/psp_verstage.c +++ b/src/soc/amd/picasso/psp_verstage/psp_verstage.c @@ -2,6 +2,7 @@ #include "psp_verstage.h" +#include <amdblocks/acpimmio.h> #include <bl_uapp/bl_syscall_public.h> #include <boot_device.h> #include <cbfs.h> @@ -237,7 +238,7 @@ void Main(void) verstage_mainboard_early_init(); svc_write_postcode(POSTCODE_LATE_INIT); - sb_enable_legacy_io(); + fch_io_enable_legacy_io(); verstage_soc_init(); verstage_mainboard_init(); diff --git a/src/soc/amd/picasso/psp_verstage/psp_verstage.h b/src/soc/amd/picasso/psp_verstage/psp_verstage.h index ef5c452500..4f85d7caa1 100644 --- a/src/soc/amd/picasso/psp_verstage/psp_verstage.h +++ b/src/soc/amd/picasso/psp_verstage/psp_verstage.h @@ -55,6 +55,5 @@ uint32_t unmap_fch_devices(void); uint32_t verstage_soc_early_init(void); void verstage_soc_init(void); uintptr_t *map_spi_rom(void); -void sb_enable_legacy_io(void); #endif /* PSP_VERSTAGE_H */ diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index bc801a34b4..3110deaa02 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -91,20 +91,6 @@ const struct irq_idx_name *sb_get_apic_reg_association(size_t *size) return irq_association; } -static void sb_enable_cf9_io(void) -{ - uint32_t reg = pm_read32(PM_DECODE_EN); - - pm_write32(PM_DECODE_EN, reg | CF9_IO_EN); -} - -static void sb_enable_legacy_io(void) -{ - uint32_t reg = pm_read32(PM_DECODE_EN); - - pm_write32(PM_DECODE_EN, reg | LEGACY_IO_EN); -} - void sb_clk_output_48Mhz(void) { u32 ctrl; @@ -131,8 +117,8 @@ void fch_pre_init(void) fch_spi_early_init(); enable_acpimmio_decode_pm04(); fch_smbus_init(); - sb_enable_cf9_io(); - sb_enable_legacy_io(); + fch_enable_cf9_io(); + fch_enable_legacy_io(); enable_aoac_devices(); sb_reset_i2c_slaves(); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 881570241a..ba23e90b58 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -200,20 +200,6 @@ static void sb_lpc_decode(void) lpc_enable_decode(tmp); } -static void sb_enable_cf9_io(void) -{ - uint32_t reg = pm_read32(PM_DECODE_EN); - - pm_write32(PM_DECODE_EN, reg | CF9_IO_EN); -} - -static void sb_enable_legacy_io(void) -{ - uint32_t reg = pm_read32(PM_DECODE_EN); - - pm_write32(PM_DECODE_EN, reg | LEGACY_IO_EN); -} - void sb_clk_output_48Mhz(u32 osc) { u32 ctrl; @@ -347,14 +333,14 @@ void bootblock_fch_early_init(void) sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */ enable_acpimmio_decode_pm04(); fch_smbus_init(); - sb_enable_cf9_io(); + fch_enable_cf9_io(); setup_spread_spectrum(&reboot); setup_misc(&reboot); if (reboot) warm_reset(); - sb_enable_legacy_io(); + fch_enable_legacy_io(); enable_aoac_devices(); } |