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-rw-r--r--src/mainboard/google/guybrush/variants/baseboard/gpio.c4
-rw-r--r--src/soc/amd/cezanne/include/soc/gpio.h4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
index 89594faf42..66b40be4dc 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c
+++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
@@ -117,7 +117,7 @@ static const struct soc_amd_gpio base_gpio_table[] = {
/* ESPI1_DATA1 */
PAD_NF(GPIO_105, SPI2_DI_ESPI2_D1, PULL_NONE),
/* ESPI1_DATA2 */
- PAD_NF(GPIO_106, EMMC_SPI2_WP_L_ESPI2_D2, PULL_NONE),
+ PAD_NF(GPIO_106, SPI2_WP_L_ESPI2_D2, PULL_NONE),
/* ESPI1_DATA3 */
PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE),
/* ESPI_ALERT_L */
@@ -217,7 +217,7 @@ static const struct soc_amd_gpio early_gpio_table[] = {
/* ESPI1_DATA1 */
PAD_NF(GPIO_105, SPI2_DI_ESPI2_D1, PULL_NONE),
/* ESPI1_DATA2 */
- PAD_NF(GPIO_106, EMMC_SPI2_WP_L_ESPI2_D2, PULL_NONE),
+ PAD_NF(GPIO_106, SPI2_WP_L_ESPI2_D2, PULL_NONE),
/* ESPI1_DATA3 */
PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE),
/* ESPI_ALERT_L */
diff --git a/src/soc/amd/cezanne/include/soc/gpio.h b/src/soc/amd/cezanne/include/soc/gpio.h
index 904c3fcc8d..d12d66771d 100644
--- a/src/soc/amd/cezanne/include/soc/gpio.h
+++ b/src/soc/amd/cezanne/include/soc/gpio.h
@@ -235,8 +235,8 @@
#define GPIO_105_IOMUX_SD0_DATA1 2
#define GPIO_105_IOMUX_GPIOxx 3
#define GPIO_106_IOMUX_LAD2 0
-#define GPIO_106_IOMUX_EMMC_SPI2_WP_L_ESPI2_D2 1
-#define GPIO_106_IOMUX_EMMC_SD0_DATA2 2
+#define GPIO_106_IOMUX_SPI2_WP_L_ESPI2_D2 1
+#define GPIO_106_IOMUX_SD0_DATA2 2
#define GPIO_106_IOMUX_GPIOxx 3
#define GPIO_107_IOMUX_LAD3 0
#define GPIO_107_IOMUX_SPI2_HOLD_L_ESPI2_D3 1