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-rw-r--r--src/mainboard/google/guybrush/mainboard.c6
-rw-r--r--src/mainboard/google/guybrush/variants/baseboard/gpio.c47
-rw-r--r--src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h3
3 files changed, 46 insertions, 10 deletions
diff --git a/src/mainboard/google/guybrush/mainboard.c b/src/mainboard/google/guybrush/mainboard.c
index e557802841..3626157338 100644
--- a/src/mainboard/google/guybrush/mainboard.c
+++ b/src/mainboard/google/guybrush/mainboard.c
@@ -176,7 +176,13 @@ static void mainboard_enable(struct device *dev)
pm_write32(PM_ESPI_INTR_CTRL, PM_ESPI_DEV_INTR_MASK & ~(BIT(1)));
}
+static void mainboard_final(void *chip_info)
+{
+ variant_finalize_gpios();
+}
+
struct chip_operations mainboard_ops = {
.init = mainboard_init,
.enable_dev = mainboard_enable,
+ .final = mainboard_final,
};
diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
index 352d0f58bf..559a86df88 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c
+++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
@@ -4,6 +4,8 @@
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <commonlib/helpers.h>
+#include <delay.h>
+#include <gpio.h>
#include <soc/gpio.h>
/* GPIO configuration in ramstage*/
@@ -31,8 +33,8 @@ static const struct soc_amd_gpio base_gpio_table[] = {
PAD_SCI(GPIO_9, PULL_NONE, EDGE_HIGH),
/* S0A3 */
PAD_NF(GPIO_10, S0A3, PULL_NONE),
- /* SOC_FP_RST_L */
- PAD_GPO(GPIO_11, HIGH),
+ /* SOC_FP_RST_L - Brought high in finalize */
+ PAD_GPO(GPIO_11, LOW),
/* SLP_S3_GATED */
PAD_GPO(GPIO_12, LOW),
/* GPIO_13 - GPIO_15: Not available */
@@ -285,6 +287,13 @@ static const struct soc_amd_gpio pcie_gpio_table[] = {
PAD_NFO(GPIO_26, PCIE_RST_L, HIGH),
};
+static const struct soc_amd_gpio gpio_fp_shutdown_table[] = {
+ /* FPMCU_RST_L */
+ PAD_GPO(GPIO_11, LOW),
+ /* EN_PWR_FP */
+ PAD_GPO(GPIO_32, LOW),
+};
+
const struct soc_amd_gpio *__weak variant_pcie_gpio_table(size_t *size)
{
*size = ARRAY_SIZE(pcie_gpio_table);
@@ -334,6 +343,11 @@ const struct soc_amd_gpio *__weak variant_early_gpio_table(size_t *size)
const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size)
{
+ if (acpi_get_sleep_type() == ACPI_S5) {
+ *size = ARRAY_SIZE(gpio_fp_shutdown_table);
+ return gpio_fp_shutdown_table;
+ }
+
*size = ARRAY_SIZE(sleep_gpio_table);
return sleep_gpio_table;
}
@@ -342,18 +356,31 @@ __weak void variant_fpmcu_reset(void)
{
if (acpi_get_sleep_type() == ACPI_S3)
return;
- /*
- * SOC_FP_RST_L line is pulled high when platform comes out of reset.
- * So, it is required to be driven low before enabling power to
- * ensure that power sequencing for the FPMCU is met.
- * However, as the FPMCU is initialized only on platform reset,
- * the reset line should not be asserted in case of S3 resume.
- */
+ /* If the system is not resuming from S3, power off the FPMCU */
static const struct soc_amd_gpio fpmcu_bootblock_table[] = {
/* SOC_FP_RST_L */
PAD_GPO(GPIO_11, LOW),
/* EN_PWR_FP */
- PAD_GPO(GPIO_32, HIGH),
+ PAD_GPO(GPIO_32, LOW),
};
program_gpios(fpmcu_bootblock_table, ARRAY_SIZE(fpmcu_bootblock_table));
}
+
+__weak void variant_finalize_gpios(void)
+{
+ static const struct soc_amd_gpio disable_fpmcu_table[] = {
+ /* FPMCU_RST_L */
+ PAD_NC(GPIO_11),
+ /* EN_PWR_FP */
+ PAD_NC(GPIO_32),
+ };
+
+ if (variant_has_fpmcu()) {
+ if (acpi_get_sleep_type() == ACPI_S3)
+ return;
+ /* Deassert the FPMCU reset to enable the FPMCU */
+ gpio_set(GPIO_11, 1); /* FPMCU_RST_L */
+ } else {
+ program_gpios(disable_fpmcu_table, ARRAY_SIZE(disable_fpmcu_table));
+ }
+}
diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
index 243f7ff884..b9a70885ed 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
@@ -39,6 +39,9 @@ const struct soc_amd_gpio *variant_pcie_gpio_table(size_t *size);
/* This function provides GPIO settings before entering sleep. */
const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size);
+/* Finalize GPIOs, such as FPMCU power */
+void variant_finalize_gpios(void);
+
void variant_fpmcu_reset(void);
bool variant_has_fpmcu(void);