diff options
| -rw-r--r-- | src/soc/nvidia/tegra210/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/stage_entry.S (renamed from src/soc/nvidia/tegra210/reset_handler.S) | 34 |
2 files changed, 29 insertions, 8 deletions
diff --git a/src/soc/nvidia/tegra210/Makefile.inc b/src/soc/nvidia/tegra210/Makefile.inc index 3b2dc7c5b1..8d7e1fce3a 100644 --- a/src/soc/nvidia/tegra210/Makefile.inc +++ b/src/soc/nvidia/tegra210/Makefile.inc @@ -101,13 +101,14 @@ ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += ../tegra/usb.c ramstage-$(CONFIG_ARM64_USE_SECURE_MONITOR) += secmon.c ramstage-$(CONFIG_HAVE_MTC) += mtc.c +ramstage-y += stage_entry.S secmon-y += cpu.c secmon-y += cpu_lib.S secmon-y += flow_ctrl.c secmon-y += power.c secmon-y += psci.c -secmon-y += reset_handler.S +secmon-y += stage_entry.S secmon-y += uart.c secmon-y += gic.c diff --git a/src/soc/nvidia/tegra210/reset_handler.S b/src/soc/nvidia/tegra210/stage_entry.S index 53622b13bf..ee0265f426 100644 --- a/src/soc/nvidia/tegra210/reset_handler.S +++ b/src/soc/nvidia/tegra210/stage_entry.S @@ -1,5 +1,8 @@ /* + * This file is part of the coreboot project. + * * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -9,19 +12,27 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <arch/asm.h> +#include <cpu/cortex_a57.h> -#define CPUACTLR_EL1 s3_1_c15_c2_0 - -CPU_RESET_ENTRY(tegra210_reset_handler) +/* + * It is observed that BTB contains stale data after power on reset. This could + * lead to unexpected branching and crashes at random intervals during the boot + * flow. Thus, invalidate the BTB immediately after power on reset. + */ +.macro t210_a57_fixup /* * Invalidate BTB along with I$ to remove any stale entries * from the branch predictor array. */ mrs x0, CPUACTLR_EL1 - orr x0, x0, #1 + orr x0, x0, #BTB_INVALIDATE msr CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */ dsb sy isb @@ -29,7 +40,7 @@ CPU_RESET_ENTRY(tegra210_reset_handler) dsb sy isb - bic x0, x0, #1 + bic x0, x0, #BTB_INVALIDATE msr CPUACTLR_EL1, x0 /* restore original CPUACTLR_EL1 */ dsb sy isb @@ -47,7 +58,7 @@ CPU_RESET_ENTRY(tegra210_reset_handler) and x0, x0, #2 /* extract oslk bit */ mrs x1, mpidr_el1 bics xzr, x0, x1, lsr #7 /* 0 if slow cluster */ - b.eq __restore_oslock + b.eq 1000f mov x0, xzr msr oslar_el1, x0 /* os lock stays 0 across warm reset */ mov x3, #3 @@ -67,9 +78,18 @@ CPU_RESET_ENTRY(tegra210_reset_handler) nop .endr -__restore_oslock: +1000: + /* Restore os lock */ mov x0, #1 msr oslar_el1, x0 +.endm + +ENTRY(stage_entry) + t210_a57_fixup + b arm64_cpu_startup +ENDPROC(stage_entry) +ENTRY(tegra210_reset_handler) + t210_a57_fixup b arm64_cpu_startup_resume ENDPROC(tegra210_reset_handler) |