diff options
| -rw-r--r-- | src/southbridge/intel/lynxpoint/chip.h | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pcie.c | 8 |
2 files changed, 10 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index a0e2232788..bb4c0048c2 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -85,6 +85,8 @@ struct southbridge_intel_lynxpoint_config { /* Enable linear PCIe Root Port function numbers starting at zero */ uint8_t pcie_port_coalesce; + /* Force root port ASPM configuration with port bitmap */ + uint8_t pcie_port_force_aspm; /* Serial IO configuration */ /* Put devices into ACPI mode instead of a PCI device */ diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index e133feb9c2..6a4d75cac2 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -495,6 +495,7 @@ static void pch_pcie_early(struct device *dev) int rp; int do_aspm; int is_lp; + struct southbridge_intel_lynxpoint_config *config = dev->chip_info; rp = root_port_number(dev); do_aspm = 0; @@ -542,6 +543,13 @@ static void pch_pcie_early(struct device *dev) } } + /* Allow ASPM to be forced on in devicetree */ + if (config && (config->pcie_port_force_aspm & (1 << (rp - 1)))) + do_aspm = 1; + + printk(BIOS_DEBUG, "PCIe Root Port %d ASPM is %sabled\n", + rp, do_aspm ? "en" : "dis"); + if (do_aspm) { /* Set ASPM bits in MPC2 register. */ pcie_update_cfg(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2)); |