diff options
| -rw-r--r-- | Documentation/mainboard/sifive/hifive-unleashed.md | 2 | ||||
| -rwxr-xr-x | util/riscv/sifive-gpt.py | 14 |
2 files changed, 14 insertions, 2 deletions
diff --git a/Documentation/mainboard/sifive/hifive-unleashed.md b/Documentation/mainboard/sifive/hifive-unleashed.md index c5c015ddc1..1d07cb7df6 100644 --- a/Documentation/mainboard/sifive/hifive-unleashed.md +++ b/Documentation/mainboard/sifive/hifive-unleashed.md @@ -11,7 +11,7 @@ For general setup instructions, please refer to the [Getting Started Guide]. The following things are still missing from this coreboot port: -- Trampoline in the MBR block to support boot mode 1 +- Support running romstage from flash (fix stack) to support boot mode 1 - CBMEM support - FU540 clock configuration - FU540 RAM init diff --git a/util/riscv/sifive-gpt.py b/util/riscv/sifive-gpt.py index cb77302528..fd82997fc6 100755 --- a/util/riscv/sifive-gpt.py +++ b/util/riscv/sifive-gpt.py @@ -25,6 +25,12 @@ BLOCK_MASK = BLOCK_SIZE - 1 # Size of the bootcode part of the MBR MBR_BOOTCODE_SIZE = 0x1be +# MBR trampoline to bootblock +MBR_BOOTCODE = bytes([ + # j pc + 0x0800 + 0x6f, 0x00, 0x10, 0x00, +]) + # A protecive MBR, without the bootcode part PROTECTIVE_MBR_FOOTER = bytes([ 0x00, 0x00, 0x02, 0x00, 0xee, 0xff, 0xff, 0xff, @@ -43,7 +49,7 @@ PROTECTIVE_MBR_FOOTER = bytes([ # [1]: https://en.wikipedia.org/wiki/GUID_Partition_Table#PROTECTIVE-MBR class ProtectiveMBR: def __init__(self): - self.bootcode = bytes(MBR_BOOTCODE_SIZE) + self.bootcode = MBR_BOOTCODE + bytes(MBR_BOOTCODE_SIZE - len(MBR_BOOTCODE)) def generate(self, stream): assert len(self.bootcode) == MBR_BOOTCODE_SIZE @@ -177,5 +183,11 @@ if __name__ == '__main__': image.fixup() + # Verify if first partition is at expected lba, otherwise trampoline will + # fail + if image.partitions[0].first_lba != 4: + print('Warning: First partition not at expected location (LBA 4)') + sys.exit(1) + with open(sys.argv[2], 'wb') as f: image.generate(f) |