diff options
| -rw-r--r-- | src/soc/intel/baytrail/acpi/globalnvs.asl | 2 | ||||
| -rw-r--r-- | src/soc/intel/braswell/acpi/globalnvs.asl | 2 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/pch/acpi/globalnvs.asl | 2 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/acpi/globalnvs.asl | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/acpi/globalnvs.asl | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/acpi/globalnvs.asl | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/acpi/globalnvs.asl | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/acpi/globalnvs.asl | 2 |
8 files changed, 8 insertions, 8 deletions
diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index 97530cb14c..3d2b3dcdd9 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -39,7 +39,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) /* Base addresses */ Offset (0x30), - CMEM, 32, /* 0x30 - CBMEM TOC */ + , 32, /* 0x30 - CBMEM TOC */ TOLM, 32, /* 0x34 - Top of Low Memory */ CBMC, 32, /* 0x38 - coreboot mem console pointer */ } diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl index 0714f23e39..22af61bc82 100644 --- a/src/soc/intel/braswell/acpi/globalnvs.asl +++ b/src/soc/intel/braswell/acpi/globalnvs.asl @@ -41,7 +41,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) /* Base addresses */ Offset (0x30), - CMEM, 32, /* 0x30 - CBMEM TOC */ + , 32, /* 0x30 - CBMEM TOC */ TOLM, 32, /* 0x34 - Top of Low Memory */ CBMC, 32, /* 0x38 - coreboot mem console pointer */ } diff --git a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl index 1911636f8d..8a6bf8787e 100644 --- a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl +++ b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl @@ -30,7 +30,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) S33G, 8, // 0x15 - Enable 3G in S3 LIDS, 8, // 0x16 - LID State PWRS, 8, // 0x17 - AC Power State - CMEM, 32, // 0x18 - 0x1b - CBMEM TOC + , 32, // 0x18 - 0x1b - CBMEM TOC CBMC, 32, // 0x1c - 0x1f - coreboot Memory Console PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit GPEI, 64, // 0x28 - 0x2f - GPE wake status bit diff --git a/src/soc/intel/denverton_ns/acpi/globalnvs.asl b/src/soc/intel/denverton_ns/acpi/globalnvs.asl index 659129f550..103397cb4d 100644 --- a/src/soc/intel/denverton_ns/acpi/globalnvs.asl +++ b/src/soc/intel/denverton_ns/acpi/globalnvs.asl @@ -38,7 +38,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) /* Base addresses */ Offset (0x30), - CMEM, 32, // 0x30 - CBMEM TOC + , 32, // 0x30 - CBMEM TOC TOLM, 32, // 0x34 - Top of Low Memory CBMC, 32, // 0x38 - coreboot mem console pointer MMOB, 32, // 0x3c - MMIO Base Low Base diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index cc7cc9c990..d5b2c20745 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -30,7 +30,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) S33G, 8, // 0x15 - Enable 3G in S3 LIDS, 8, // 0x16 - LID State PWRS, 8, // 0x17 - AC Power State - CMEM, 32, // 0x18 - 0x1b - CBMEM TOC + , 32, // 0x18 - 0x1b - CBMEM TOC CBMC, 32, // 0x1c - 0x1f - coreboot Memory Console PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit GPEI, 64, // 0x28 - 0x2f - GPE wake status bit diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index f64a845238..e873f55375 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -59,7 +59,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) S3U0, 8, // 0x35 - Enable USB0 in S3 S3U1, 8, // 0x36 - Enable USB1 in S3 S33G, 8, // 0x37 - Enable 3G in S3 - CMEM, 32, // 0x38 - CBMEM TOC + , 32, // 0x38 - CBMEM TOC /* Integrated Graphics Device */ Offset (0x3c), IGDS, 8, // 0x3c - IGD state (primary = 1) diff --git a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl index 51f6935c87..949da74d8c 100644 --- a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl +++ b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl @@ -59,7 +59,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) S3U0, 8, // 0x35 - Enable USB0 in S3 S3U1, 8, // 0x36 - Enable USB1 in S3 S33G, 8, // 0x37 - Enable 3G in S3 - CMEM, 32, // 0x38 - CBMEM TOC + , 32, // 0x38 - CBMEM TOC /* Integrated Graphics Device */ Offset (0x3c), IGDS, 8, // 0x3c - IGD state (primary = 1) diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index f4071f1144..979e084161 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -59,7 +59,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) S3U0, 8, // 0x35 - Enable USB0 in S3 S3U1, 8, // 0x36 - Enable USB1 in S3 S33G, 8, // 0x37 - Enable 3G in S3 - CMEM, 32, // 0x38 - CBMEM TOC + , 32, // 0x38 - CBMEM TOC /* Integrated Graphics Device */ Offset (0x3c), IGDS, 8, // 0x3c - IGD state (primary = 1) |