diff options
| -rw-r--r-- | src/mainboard/getac/p470/romstage.c | 15 | ||||
| -rw-r--r-- | src/mainboard/ibase/mb899/romstage.c | 16 | ||||
| -rw-r--r-- | src/mainboard/intel/d945gclf/romstage.c | 17 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/romstage.c | 17 | ||||
| -rw-r--r-- | src/mainboard/lenovo/t60/romstage.c | 17 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x60/romstage.c | 17 | ||||
| -rw-r--r-- | src/mainboard/roda/rk886ex/romstage.c | 17 |
7 files changed, 0 insertions, 116 deletions
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 0f746e1b75..b0dd2bc544 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -340,21 +340,6 @@ void main(unsigned long bist) /* Initialize the internal PCIe links before we go into stage2 */ i945_late_initialization(); -#if !CONFIG_HAVE_ACPI_RESUME - /* When doing resume, we must not overwrite RAM */ -#if CONFIG_DEBUG_RAM_SETUP - sdram_dump_mchbar_registers(); - - { - /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); - - printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); - ram_check(0x00000000, 0x000a0000); - ram_check(0x00100000, tom); - } -#endif -#endif MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_recovery(boot_mode==2); diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 2ee45fead9..0e74418981 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -291,22 +291,6 @@ void main(unsigned long bist) /* Initialize the internal PCIe links before we go into stage2 */ i945_late_initialization(); -#if !CONFIG_HAVE_ACPI_RESUME -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 -#if CONFIG_DEBUG_RAM_SETUP - sdram_dump_mchbar_registers(); -#endif - - { - /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); - - printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); - ram_check(0x00000000, 0x000a0000); - //ram_check(0x00100000, tom); - } -#endif -#endif quick_ram_check(); diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 1ae632debc..586e03502e 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -251,23 +251,6 @@ void main(unsigned long bist) /* Initialize the internal PCIe links before we go into stage2 */ i945_late_initialization(); -#if !CONFIG_HAVE_ACPI_RESUME -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 -#if CONFIG_DEBUG_RAM_SETUP - sdram_dump_mchbar_registers(); -#endif - - { - /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); - - printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); - ram_check(0x00000000, 0x000a0000); - //ram_check(0x00100000, tom); - } -#endif -#endif - MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_recovery(boot_mode==2); diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 06a74c420c..9c76a420ba 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -402,23 +402,6 @@ void main(unsigned long bist) /* Initialize the internal PCIe links before we go into stage2 */ i945_late_initialization(); -#if !CONFIG_HAVE_ACPI_RESUME -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 -#if CONFIG_DEBUG_RAM_SETUP - sdram_dump_mchbar_registers(); -#endif - - { - /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); - - printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); - ram_check(0x00000000, 0x000a0000); - //ram_check(0x00100000, tom); - } -#endif -#endif - quick_ram_check(); MCHBAR16(SSKPD) = 0xCAFE; diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 9c7f62486c..1e2b72d6b7 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -302,23 +302,6 @@ void main(unsigned long bist) /* Initialize the internal PCIe links before we go into stage2 */ i945_late_initialization(); -#if !CONFIG_HAVE_ACPI_RESUME -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 -#if CONFIG_DEBUG_RAM_SETUP - sdram_dump_mchbar_registers(); - - { - /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); - - printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); - ram_check(0x00000000, 0x000a0000); - ram_check(0x00100000, tom); - } -#endif -#endif -#endif - MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_recovery(boot_mode==2); diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 1d9f68b5f2..d1f8f640a2 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -304,23 +304,6 @@ void main(unsigned long bist) /* Initialize the internal PCIe links before we go into stage2 */ i945_late_initialization(); -#if !CONFIG_HAVE_ACPI_RESUME -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 -#if CONFIG_DEBUG_RAM_SETUP - sdram_dump_mchbar_registers(); - - { - /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), 0x5c); - - printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); - ram_check(0x00000000, 0x000a0000); - ram_check(0x00100000, tom); - } -#endif -#endif -#endif - MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_recovery(boot_mode==2); diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index e8bbb14f2d..1bea48c875 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -327,23 +327,6 @@ void main(unsigned long bist) /* Initialize the internal PCIe links before we go into stage2 */ i945_late_initialization(); -#if !CONFIG_HAVE_ACPI_RESUME -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 -#if CONFIG_DEBUG_RAM_SETUP - sdram_dump_mchbar_registers(); - - { - /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); - - printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); - ram_check(0x00000000, 0x000a0000); - ram_check(0x00100000, tom); - } -#endif -#endif -#endif - MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_recovery(boot_mode==2); |