diff options
| -rw-r--r-- | src/soc/intel/cannonlake/acpi/cnvi.asl | 32 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/acpi/southbridge.asl | 3 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/pm.h | 22 |
3 files changed, 48 insertions, 9 deletions
diff --git a/src/soc/intel/cannonlake/acpi/cnvi.asl b/src/soc/intel/cannonlake/acpi/cnvi.asl new file mode 100644 index 0000000000..f9aeeb06e0 --- /dev/null +++ b/src/soc/intel/cannonlake/acpi/cnvi.asl @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/pm.h> + +/* CNVi Controller 0:14.3 */ +Device (CNVI) { + Name(_ADR, 0x00140003) + + Name (_S3D, 3) /* D3 supported in S3 */ + Name (_S0W, 3) /* D3 can wake device in S0 */ + Name (_S3W, 3) /* D3 can wake system from S3 */ + + Name (_PRW, Package() { PME_B0_EN_BIT, 3 }) + + Method (_STA, 0) + { + Return (0xF) + } +} diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index fdba171ada..d0d03f0ac3 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -45,3 +45,6 @@ /* PCI _OSC */ #include <soc/intel/common/acpi/pci_osc.asl> + +/* CNVi */ +#include "cnvi.asl" diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h index 378fac9139..1494d561d8 100644 --- a/src/soc/intel/cannonlake/include/soc/pm.h +++ b/src/soc/intel/cannonlake/include/soc/pm.h @@ -17,14 +17,6 @@ #ifndef _SOC_PM_H_ #define _SOC_PM_H_ -#include <arch/acpi.h> -#include <arch/io.h> -#include <compiler.h> -#include <soc/gpe.h> -#include <soc/iomap.h> -#include <soc/smbus.h> -#include <soc/pmc.h> - #define PM1_STS 0x00 #define WAK_STS (1 << 15) #define PCIEXPWAK_STS (1 << 14) @@ -116,7 +108,8 @@ #define WADT_EN (1 << 18) #define GPIO_T2_EN (1 << 15) #define ESPI_EN (1 << 14) -#define PME_B0_EN (1 << 13) +#define PME_B0_EN_BIT 13 +#define PME_B0_EN (1 << PME_B0_EN_BIT) #define ME_SCI_EN (1 << 12) #define PME_EN (1 << 11) #define BATLOW_EN (1 << 10) @@ -145,6 +138,16 @@ #define PSS_LATENCY_TRANSITION 10 #define PSS_LATENCY_BUSMASTER 10 +#if !defined(__ACPI__) + +#include <arch/acpi.h> +#include <arch/io.h> +#include <compiler.h> +#include <soc/gpe.h> +#include <soc/iomap.h> +#include <soc/smbus.h> +#include <soc/pmc.h> + struct chipset_power_state { uint16_t pm1_sts; uint16_t pm1_en; @@ -168,4 +171,5 @@ uint16_t smbus_tco_regs(void); /* Set the DISB after DRAM init */ void pmc_set_disb(void); +#endif /* !defined(__ACPI__) */ #endif |