diff options
| -rw-r--r-- | src/mainboard/google/octopus/variants/baseboard/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/starlabs/lite/variants/glk/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/starlabs/lite/variants/glkr/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/chip.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/chip.h | 2 |
5 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index fdfcd61f51..c6bfe54e65 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -290,5 +290,5 @@ chip soc/intel/apollolake # FSP UPD to modify the Integrated Filter (IF) value # Set it to default value: 0x12 - register "ModPhyIfValue" = "0x12" + register "mod_phy_if_value" = "0x12" end diff --git a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb index abfbc0a6f6..2f58a7b5e5 100644 --- a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb @@ -26,7 +26,7 @@ chip soc/intel/apollolake register "pnp_settings" = "PNP_PERF_POWER" - register "ModPhyIfValue" = "0x12" + register "mod_phy_if_value" = "0x12" register "prt0_gpio" = "GPIO_PRT0_UDEF" diff --git a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb index 3102b1fe29..fe32143c5d 100644 --- a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb @@ -26,7 +26,7 @@ chip soc/intel/apollolake register "pnp_settings" = "PNP_PERF_POWER" - register "ModPhyIfValue" = "0x12" + register "mod_phy_if_value" = "0x12" register "prt0_gpio" = "GPIO_PRT0_UDEF" diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index e3bfa1e273..a29ba3b19f 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -612,7 +612,7 @@ static void glk_fsp_silicon_init_params_cb( /* * Options to change USB3 ModPhy setting for Integrated Filter value. */ - silconfig->ModPhyIfValue = cfg->ModPhyIfValue; + silconfig->ModPhyIfValue = cfg->mod_phy_if_value; /* * Options to bump USB3 LDO voltage with 40mv. diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index c1bc0209dc..26e4478da2 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -190,7 +190,7 @@ struct soc_intel_apollolake_config { * value. Default is 0 to not changing default IF value (0x12). Set * value with the range from 0x01 to 0xff to change IF value. */ - uint8_t ModPhyIfValue; + uint8_t mod_phy_if_value; /* Options to bump USB3 LDO voltage. Default is FALSE to not increasing * LDO voltage. Set TRUE to increase LDO voltage with 40mV. |