diff options
| -rw-r--r-- | src/soc/intel/common/Kconfig | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/reset.c | 54 |
3 files changed, 60 insertions, 0 deletions
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index aadd64d0b5..1dce4e3a6c 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -21,3 +21,7 @@ config MRC_SETTINGS_PROTECT endif # CACHE_MRC_SETTINGS endif # HAVE_MRC + +config SOC_INTEL_COMMON_RESET + bool + default n diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 0c39d80340..d340308992 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -2,3 +2,5 @@ ramstage-y += hda_verb.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c +romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c new file mode 100644 index 0000000000..2046c3beda --- /dev/null +++ b/src/soc/intel/common/reset.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/hlt.h> +#include <arch/io.h> +#include <reset.h> + +/* Reset control port */ +#define RST_CNT 0xcf9 +#define FULL_RST (1 << 3) +#define RST_CPU (1 << 2) +#define SYS_RST (1 << 1) + +void hard_reset(void) +{ + /* S0->S5->S0 trip. */ + outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT); + while (1) + hlt(); +} + +void soft_reset(void) +{ + /* PMC_PLTRST# asserted. */ + outb(RST_CPU | SYS_RST, RST_CNT); + while (1) + hlt(); +} + +void cpu_reset(void) +{ + /* Sends INIT# to CPU */ + outb(RST_CPU, RST_CNT); + while (1) + hlt(); +} |