diff options
-rw-r--r-- | src/soc/intel/common/block/cpu/cpulib.c | 24 | ||||
-rw-r--r-- | src/soc/intel/common/block/include/intelblocks/cpulib.h | 7 | ||||
-rw-r--r-- | src/soc/intel/common/block/include/intelblocks/msr.h | 1 |
3 files changed, 32 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index e1bd471adf..0b91860dfd 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -3,12 +3,15 @@ #include <assert.h> #include <acpi/acpigen.h> #include <console/console.h> +#include <cpu/intel/common/common.h> #include <cpu/intel/turbo.h> #include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> #include <arch/cpu.h> #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> #include <intelblocks/msr.h> +#include <smp/node.h> #include <soc/soc_chip.h> #include <types.h> @@ -477,3 +480,24 @@ void get_cpu_topology_from_apicid(uint32_t apicid, uint8_t *package, if (thread) *thread = apicid & ((1 << thread_bits) - 1); } + +static void sync_core_prmrr(void) +{ + static msr_t msr_base, msr_mask; + + if (boot_cpu()) { + msr_base = rdmsr(MSR_PRMRR_BASE_0); + msr_mask = rdmsr(MSR_PRMRR_PHYS_MASK); + } else if (!intel_ht_sibling()) { + wrmsr(MSR_PRMRR_BASE_0, msr_base); + wrmsr(MSR_PRMRR_PHYS_MASK, msr_mask); + } +} + +void init_core_prmrr(void) +{ + msr_t msr = rdmsr(MTRR_CAP_MSR); + + if (msr.lo & MTRR_CAP_PRMRR) + sync_core_prmrr(); +} diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index 281c9651a1..0d489f4190 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -187,4 +187,11 @@ void enable_pm_timer_emulation(void); void get_cpu_topology_from_apicid(uint32_t apicid, uint8_t *package, uint8_t *core, uint8_t *thread); +/* + * Initialize core PRMRR + * + * Read the BSP PRMRR snapshot and apply on the rest of the core threads + */ +void init_core_prmrr(void); + #endif /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 41440488f4..8e56aa325b 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -48,6 +48,7 @@ #define MSR_PRMRR_VALID_CONFIG 0x1fb #define MSR_POWER_CTL 0x1fc #define POWER_CTL_C1E_MASK (1 << 1) +#define MSR_PRMRR_BASE_0 0x2a0 #define MSR_EVICT_CTL 0x2e0 #define MSR_LT_CONTROL 0x2e7 #define LT_CONTROL_LOCK (1 << 0) |