diff options
| -rw-r--r-- | src/mainboard/pcengines/apu2/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/mainboard/pcengines/apu2/mainboard.c | 20 |
2 files changed, 20 insertions, 1 deletions
diff --git a/src/mainboard/pcengines/apu2/Makefile.inc b/src/mainboard/pcengines/apu2/Makefile.inc index e1a5f8d018..77c6d789c3 100644 --- a/src/mainboard/pcengines/apu2/Makefile.inc +++ b/src/mainboard/pcengines/apu2/Makefile.inc @@ -19,6 +19,7 @@ romstage-y += gpio_ftns.c ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c +ramstage-y += gpio_ftns.c ## DIMM SPD for on-board memory SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index 98fe8ddf4a..742135571a 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -28,9 +28,11 @@ #include <northbridge/amd/pi/00730F01/pci_devs.h> #include <southbridge/amd/common/amd_pci_util.h> #include <superio/nuvoton/nct5104d/nct5104d.h> - +#include <smbios.h> +#include <string.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> +#include "gpio_ftns.h" #define SPD_SIZE 128 #define PM_RTC_CONTROL 0x56 @@ -188,6 +190,22 @@ static void mainboard_enable(device_t dev) pirq_setup(); } +/* + * We will stuff the memory size into the smbios sku location. + */ +const char *smbios_mainboard_sku(void) +{ + static char sku[5]; + if (sku[0] != 0) + return sku; + + if (!get_spd_offset()) + snprintf(sku, sizeof(sku), "2 GB"); + else + snprintf(sku, sizeof(sku), "4 GB"); + return sku; +} + struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; |