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-rw-r--r--src/mainboard/intel/frost_creek/Kconfig30
-rw-r--r--src/mainboard/intel/frost_creek/Kconfig.name2
-rw-r--r--src/mainboard/intel/frost_creek/Makefile.mk9
-rw-r--r--src/mainboard/intel/frost_creek/acpi_tables.c8
-rw-r--r--src/mainboard/intel/frost_creek/board.fmd9
-rw-r--r--src/mainboard/intel/frost_creek/board_id.c13
-rw-r--r--src/mainboard/intel/frost_creek/board_id.h8
-rw-r--r--src/mainboard/intel/frost_creek/board_info.txt6
-rw-r--r--src/mainboard/intel/frost_creek/devicetree.cb5
-rw-r--r--src/mainboard/intel/frost_creek/dsdt.asl24
-rw-r--r--src/mainboard/intel/frost_creek/gpio.c227
-rw-r--r--src/mainboard/intel/frost_creek/ramstage.c17
-rw-r--r--src/mainboard/intel/frost_creek/ramstage.h10
-rw-r--r--src/mainboard/intel/frost_creek/romstage.c47
-rw-r--r--src/mainboard/intel/frost_creek/romstage.h11
15 files changed, 426 insertions, 0 deletions
diff --git a/src/mainboard/intel/frost_creek/Kconfig b/src/mainboard/intel/frost_creek/Kconfig
new file mode 100644
index 0000000000..f93ab78694
--- /dev/null
+++ b/src/mainboard/intel/frost_creek/Kconfig
@@ -0,0 +1,30 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_INTEL_FROST_CREEK
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select SOC_INTEL_SNOWRIDGE
+ select BOARD_ROMSIZE_KB_32768
+ select HAVE_ACPI_TABLES
+ select NO_UART_ON_SUPERIO
+
+config MAINBOARD_DIR
+ default "intel/frost_creek"
+
+config MAINBOARD_PART_NUMBER
+ default "Frost Creek"
+
+config FMDFILE
+ default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd"
+
+config CBFS_SIZE
+ default 0xc00000
+
+config DIMM_MAX
+ default 4
+
+config DIMM_SPD_SIZE
+ default 512
+
+endif # BOARD_INTEL_FROST_CREEK
diff --git a/src/mainboard/intel/frost_creek/Kconfig.name b/src/mainboard/intel/frost_creek/Kconfig.name
new file mode 100644
index 0000000000..384e9dfffe
--- /dev/null
+++ b/src/mainboard/intel/frost_creek/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_INTEL_FROST_CREEK
+ bool "Frost Creek"
diff --git a/src/mainboard/intel/frost_creek/Makefile.mk b/src/mainboard/intel/frost_creek/Makefile.mk
new file mode 100644
index 0000000000..272c5a33f4
--- /dev/null
+++ b/src/mainboard/intel/frost_creek/Makefile.mk
@@ -0,0 +1,9 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+romstage-y += board_id.c
+romstage-y += gpio.c
+
+ramstage-y += board_id.c
+ramstage-y += ramstage.c
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/
diff --git a/src/mainboard/intel/frost_creek/acpi_tables.c b/src/mainboard/intel/frost_creek/acpi_tables.c
new file mode 100644
index 0000000000..b6e3846f28
--- /dev/null
+++ b/src/mainboard/intel/frost_creek/acpi_tables.c
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+
+void mainboard_fill_fadt(acpi_fadt_t *fadt)
+{
+ fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER;
+}
diff --git a/src/mainboard/intel/frost_creek/board.fmd b/src/mainboard/intel/frost_creek/board.fmd
new file mode 100644
index 0000000000..5c22e12d52
--- /dev/null
+++ b/src/mainboard/intel/frost_creek/board.fmd
@@ -0,0 +1,9 @@
+FLASH@0xfe000000 0x02000000 {
+ BIOS@0x01400000 0x00C00000 {
+ RW_MRC_CACHE 0x10000
+ SMMSTORE 0x40000
+ RW_KTI_CACHE 0x1000
+ FMAP 0x200
+ COREBOOT(CBFS)
+ }
+}
diff --git a/src/mainboard/intel/frost_creek/board_id.c b/src/mainboard/intel/frost_creek/board_id.c
new file mode 100644
index 0000000000..a9d30497be
--- /dev/null
+++ b/src/mainboard/intel/frost_creek/board_id.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boardid.h>
+#include <console/console.h>
+
+#include "board_id.h"
+
+uint32_t board_id(void)
+{
+ printk(BIOS_SPEW, "Board ID: 0x%x\n", BOARD_ID_FROST_CREEK);
+
+ return BOARD_ID_FROST_CREEK;
+}
diff --git a/src/mainboard/intel/frost_creek/board_id.h b/src/mainboard/intel/frost_creek/board_id.h
new file mode 100644
index 0000000000..7a68474dce
--- /dev/null
+++ b/src/mainboard/intel/frost_creek/board_id.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _MAINBOARD_FROST_CREEK_BOARD_ID_H_
+#define _MAINBOARD_FROST_CREEK_BOARD_ID_H_
+
+#define BOARD_ID_FROST_CREEK 0x52
+
+#endif // _MAINBOARD_FROST_CREEK_BOARD_ID_H_
diff --git a/src/mainboard/intel/frost_creek/board_info.txt b/src/mainboard/intel/frost_creek/board_info.txt
new file mode 100644
index 0000000000..1b338abfad
--- /dev/null
+++ b/src/mainboard/intel/frost_creek/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Intel
+Board name: Frost Creek
+Category: eval
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/intel/frost_creek/devicetree.cb b/src/mainboard/intel/frost_creek/devicetree.cb
new file mode 100644
index 0000000000..9f8f1a0dfc
--- /dev/null
+++ b/src/mainboard/intel/frost_creek/devicetree.cb
@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/snowridge
+ device domain 0 on end
+end
diff --git a/src/mainboard/intel/frost_creek/dsdt.asl b/src/mainboard/intel/frost_creek/dsdt.asl
new file mode 100644
index 0000000000..7efa113b71
--- /dev/null
+++ b/src/mainboard/intel/frost_creek/dsdt.asl
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock (
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20240225 /* OEM revision */
+)
+{
+ #include <acpi/dsdt_top.asl>
+
+ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ /* SNR ACPI tables */
+ #include <soc/intel/snowridge/acpi/uncore.asl>
+
+ #include <soc/intel/snowridge/acpi/southcluster.asl>
+}
diff --git a/src/mainboard/intel/frost_creek/gpio.c b/src/mainboard/intel/frost_creek/gpio.c
new file mode 100644
index 0000000000..bbd6e8ba38
--- /dev/null
+++ b/src/mainboard/intel/frost_creek/gpio.c
@@ -0,0 +1,227 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio_snr.h>
+
+#include "romstage.h"
+
+static struct snr_pad_config frost_creek_gpio_table[] = {
+ SNR_PAD_CFG_STRUCT0(GPIO_WEST2_4, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK,
+ GPIO_HOSTSW_OWN_DEFAULT),
+ SNR_PAD_CFG_STRUCT0(GPIO_WEST2_5, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK,
+ GPIO_HOSTSW_OWN_DEFAULT),
+ SNR_PAD_CFG_STRUCT0(GPIO_WEST2_6, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK,
+ GPIO_HOSTSW_OWN_DEFAULT),
+ SNR_PAD_CFG_STRUCT0(GPIO_WEST2_7, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK,
+ GPIO_HOSTSW_OWN_DEFAULT),
+ SNR_PAD_CFG_STRUCT0(GPIO_WEST2_8, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK,
+ GPIO_HOSTSW_OWN_DEFAULT),
+ SNR_PAD_CFG_STRUCT0(GPIO_WEST2_9, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK,
+ GPIO_HOSTSW_OWN_DEFAULT),
+ SNR_PAD_CFG_STRUCT0(GPIO_WEST2_10, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK,
+ GPIO_HOSTSW_OWN_DEFAULT),
+ SNR_PAD_CFG_STRUCT0(GPIO_WEST2_11, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK,
+ GPIO_HOSTSW_OWN_DEFAULT),
+ SNR_PAD_CFG_STRUCT0(GPIO_WEST2_18,
+ PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE,
+ PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE |
+ PAD_CFG0_TX_STATE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(GPIO_WEST2_19,
+ PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE,
+ PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE |
+ PAD_CFG0_TX_STATE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(GPIO_WEST2_20,
+ PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE,
+ PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE |
+ PAD_CFG0_TX_STATE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(GPIO_WEST01_0,
+ PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE,
+ PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE |
+ PAD_CFG0_TX_STATE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(GPIO_WEST01_1, PAD_FUNC(GPIO), PAD_CFG0_MODE_MASK,
+ GPIO_HOSTSW_OWN_DEFAULT),
+ SNR_PAD_CFG_STRUCT0(GPIO_WEST01_4,
+ PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE,
+ PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE |
+ PAD_CFG0_TX_STATE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(GPIO_WEST01_5,
+ PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE,
+ PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE |
+ PAD_CFG0_TX_STATE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(GPIO_WEST01_6,
+ PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE,
+ PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE |
+ PAD_CFG0_TX_STATE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(GPIO_WEST01_7,
+ PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE,
+ PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE |
+ PAD_CFG0_TX_STATE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(GPIO_WEST01_8,
+ PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE,
+ PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE |
+ PAD_CFG0_TX_STATE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(GPIO_WEST01_9,
+ PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE,
+ PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE |
+ PAD_CFG0_TX_STATE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(GPIO_WEST01_10,
+ PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE,
+ PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE |
+ PAD_CFG0_TX_STATE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(GPIO_WEST01_11, PAD_FUNC(GPIO) | PAD_BUF(TX_DISABLE),
+ PAD_CFG0_RXINV_MASK | PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE |
+ PAD_CFG0_TX_DISABLE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(GPIO_WEST5_15, PAD_FUNC(GPIO) | PAD_BUF(TX_DISABLE),
+ PAD_CFG0_RXINV_MASK | PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE |
+ PAD_CFG0_TX_DISABLE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(GPIO_WEST5_16,
+ PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE,
+ PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE |
+ PAD_CFG0_TX_STATE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(GPIO_WEST5_17,
+ PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE,
+ PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE |
+ PAD_CFG0_TX_STATE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(GPIO_WEST5_18,
+ PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE,
+ PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE |
+ PAD_CFG0_TX_STATE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(GPIO_WESTB_8, PAD_FUNC(GPIO) | PAD_BUF(TX_DISABLE),
+ PAD_CFG0_RXINV_MASK | PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE |
+ PAD_CFG0_TX_DISABLE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(
+ GPIO_WESTB_11,
+ PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(SCI) | PAD_FUNC(GPIO) | PAD_BUF(TX_DISABLE),
+ PAD_CFG0_RXINV_MASK | PAD_CFG0_TRIG_MASK | PAD_CFG0_ROUTE_MASK |
+ PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(GPIO_EAST2_6,
+ PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE,
+ PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE |
+ PAD_CFG0_TX_STATE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(GPIO_EAST2_10,
+ PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE,
+ PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE |
+ PAD_CFG0_TX_STATE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(GPIO_EAST2_11,
+ PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE,
+ PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE |
+ PAD_CFG0_TX_STATE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(
+ GPIO_EAST2_12,
+ PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(IOAPIC) | PAD_FUNC(GPIO) | PAD_BUF(TX_DISABLE),
+ PAD_CFG0_TRIG_MASK | PAD_CFG0_RXINV_MASK | PAD_CFG0_ROUTE_MASK |
+ PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(GPIO_EAST2_13, PAD_FUNC(GPIO) | PAD_BUF(TX_DISABLE),
+ PAD_CFG0_RXINV_MASK | PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE |
+ PAD_CFG0_TX_DISABLE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(GPIO_EAST2_14,
+ PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE,
+ PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE |
+ PAD_CFG0_TX_STATE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(GPIO_EAST2_17,
+ PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE,
+ PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE |
+ PAD_CFG0_TX_STATE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(GPIO_EAST2_18,
+ PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE,
+ PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE |
+ PAD_CFG0_TX_STATE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(GPIO_EAST2_19,
+ PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE,
+ PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE |
+ PAD_CFG0_TX_STATE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(GPIO_EAST2_20,
+ PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE,
+ PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE |
+ PAD_CFG0_TX_STATE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(GPIO_EAST2_22, PAD_FUNC(GPIO) | PAD_BUF(TX_DISABLE),
+ PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(GPIO_EAST2_23,
+ PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE,
+ PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE |
+ PAD_CFG0_TX_STATE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(GPIO_EAST0_10,
+ PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE,
+ PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE |
+ PAD_CFG0_TX_STATE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(GPIO_EAST0_11,
+ PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE,
+ PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE |
+ PAD_CFG0_TX_STATE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(GPIO_EAST0_18,
+ PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE,
+ PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE |
+ PAD_CFG0_TX_STATE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT0(GPIO_EAST0_19, PAD_FUNC(GPIO), PAD_CFG0_MODE_MASK,
+ GPIO_HOSTSW_OWN_DEFAULT),
+ SNR_PAD_CFG_STRUCT0(GPIO_EAST0_21,
+ PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE,
+ PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE |
+ PAD_CFG0_TX_STATE,
+ GPIO_HOSTSW_OWN_DRIVER),
+ SNR_PAD_CFG_STRUCT1(GPIO_EMMC_0, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK, PAD_PULL(UP_20K),
+ PAD_CFG1_PULL_MASK, GPIO_HOSTSW_OWN_DEFAULT),
+ SNR_PAD_CFG_STRUCT1(GPIO_EMMC_1, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK, PAD_PULL(DN_20K),
+ PAD_CFG1_PULL_MASK, GPIO_HOSTSW_OWN_DEFAULT),
+ SNR_PAD_CFG_STRUCT1(GPIO_EMMC_2, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK, PAD_PULL(UP_20K),
+ PAD_CFG1_PULL_MASK, GPIO_HOSTSW_OWN_DEFAULT),
+ SNR_PAD_CFG_STRUCT1(GPIO_EMMC_3, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK, PAD_PULL(UP_20K),
+ PAD_CFG1_PULL_MASK, GPIO_HOSTSW_OWN_DEFAULT),
+ SNR_PAD_CFG_STRUCT1(GPIO_EMMC_4, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK, PAD_PULL(UP_20K),
+ PAD_CFG1_PULL_MASK, GPIO_HOSTSW_OWN_DEFAULT),
+ SNR_PAD_CFG_STRUCT1(GPIO_EMMC_5, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK, PAD_PULL(UP_20K),
+ PAD_CFG1_PULL_MASK, GPIO_HOSTSW_OWN_DEFAULT),
+ SNR_PAD_CFG_STRUCT1(GPIO_EMMC_6, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK, PAD_PULL(UP_20K),
+ PAD_CFG1_PULL_MASK, GPIO_HOSTSW_OWN_DEFAULT),
+ SNR_PAD_CFG_STRUCT1(GPIO_EMMC_7, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK, PAD_PULL(UP_20K),
+ PAD_CFG1_PULL_MASK, GPIO_HOSTSW_OWN_DEFAULT),
+ SNR_PAD_CFG_STRUCT1(GPIO_EMMC_8, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK, PAD_PULL(UP_20K),
+ PAD_CFG1_PULL_MASK, GPIO_HOSTSW_OWN_DEFAULT),
+ SNR_PAD_CFG_STRUCT1(GPIO_EMMC_9, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK, PAD_PULL(UP_20K),
+ PAD_CFG1_PULL_MASK, GPIO_HOSTSW_OWN_DEFAULT),
+ SNR_PAD_CFG_STRUCT1(GPIO_EMMC_10, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK, PAD_PULL(UP_20K),
+ PAD_CFG1_PULL_MASK, GPIO_HOSTSW_OWN_DEFAULT)
+};
+
+void mainboard_config_gpios(void)
+{
+ printk(BIOS_INFO, "GPIO table: %p, entry num: %zu!\n", frost_creek_gpio_table,
+ ARRAY_SIZE(frost_creek_gpio_table));
+ /**
+ * Configure pads prior to FspSiliconInit() in case there's any
+ * dependencies during hardware initialization.
+ */
+ gpio_configure_snr_pads(frost_creek_gpio_table, ARRAY_SIZE(frost_creek_gpio_table));
+}
diff --git a/src/mainboard/intel/frost_creek/ramstage.c b/src/mainboard/intel/frost_creek/ramstage.c
new file mode 100644
index 0000000000..fe112fbd6e
--- /dev/null
+++ b/src/mainboard/intel/frost_creek/ramstage.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <ramstage.h>
+
+void mainboard_silicon_init_params(FSPS_UPD *supd)
+{
+ /**
+ * Default eMMC DLL configuration.
+ */
+ static BL_SCS_SD_DLL frost_creek_emmc_config = {0x00000500, 0x00000910, 0x2a2b292a,
+ 0x1c1d251c, 0x0001000c, 0x00001818};
+
+ supd->FspsConfig.PcdEMMCDLLConfigPtr = (UINT32)&frost_creek_emmc_config;
+ printk(BIOS_DEBUG, "[cb] PcdEMMCDLLConfigPtr: 0x%08x\n",
+ supd->FspsConfig.PcdEMMCDLLConfigPtr);
+}
diff --git a/src/mainboard/intel/frost_creek/ramstage.h b/src/mainboard/intel/frost_creek/ramstage.h
new file mode 100644
index 0000000000..50dc0d69b7
--- /dev/null
+++ b/src/mainboard/intel/frost_creek/ramstage.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _MAINBOARD_FROST_CREEK_RAMSTAGE_H_
+#define _MAINBOARD_FROST_CREEK_RAMSTAGE_H_
+
+#include <fsp/soc_binding.h>
+
+void mainboard_silicon_init_params(FSPS_UPD *supd);
+
+#endif // _MAINBOARD_FROST_CREEK_RAMSTAGE_H_
diff --git a/src/mainboard/intel/frost_creek/romstage.c b/src/mainboard/intel/frost_creek/romstage.c
new file mode 100644
index 0000000000..ebf39436cc
--- /dev/null
+++ b/src/mainboard/intel/frost_creek/romstage.c
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdint.h>
+
+#include "romstage.h"
+
+static void mainboard_hsio_config_params(FSPM_UPD *mupd)
+{
+ static BL_HSIO_INFORMATION high_speed_io_config;
+
+ /**
+ * HSIO lanes are shared by PCH PCIe root ports, SATA ports and USB port, just leave it as default.
+ */
+ for (uint8_t lane = 0; lane < BL_MAX_FIA_LANES; lane++) {
+ high_speed_io_config.FiaLaneConfig[lane] = BL_FIA_LANE_OVERRIDE_DISABLED;
+ high_speed_io_config.FiaLaneLinkWidth[lane] =
+ BL_FIA_LANE_PCIE_ROOT_PORT_LINK_WIDTH_SET_BY_BICTRL;
+ }
+
+ mupd->FspmConfig.PcdFiaLaneConfigPtr = (uint32_t)&high_speed_io_config;
+}
+
+static void mainboard_pcie_init(FSPM_UPD *mupd)
+{
+ /**
+ * The following UPD value are related to port bifurcation and hot plug:
+ * 1. `mupd->FspmConfig.PcdIIOPciePortBifurcation,
+ * 2. `mupd->FspmConfig.PcdIIoPciePort1[ABCD]HPCapable`,
+ * 3. `mupd->FspmConfig.PcdIIoPciePort1[ABCD]HPSurprise`,
+ * 4. `mupd->FspmConfig.PcdBifurcationPcie[02]` and
+ * 5. `mupd->FspmConfig.PcdPcieHotPlugEnable`.
+ *
+ * For example, if the `mupd->FspmConfig.PcdIIOPciePortBifurcation` is 0 (x4x4x4x4), then
+ * set `mupd->FspmConfig.PcdIIoPciePort1[ABCD]HPCapable` and `mupd->FspmConfig.PcdIIoPciePort1[ABCD]HPSurprise`
+ * to enable hot plug capable and surprise on each Root Port.
+ *
+ * For PCH PCIe Root Port, item 4 and 5 are used.
+ */
+}
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ mainboard_hsio_config_params(mupd);
+
+ if (CONFIG(PCIEXP_HOTPLUG))
+ mainboard_pcie_init(mupd);
+}
diff --git a/src/mainboard/intel/frost_creek/romstage.h b/src/mainboard/intel/frost_creek/romstage.h
new file mode 100644
index 0000000000..3b4a2acfcf
--- /dev/null
+++ b/src/mainboard/intel/frost_creek/romstage.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _MAINBOARD_FROST_CREEK_ROMSTAGE_H_
+#define _MAINBOARD_FROST_CREEK_ROMSTAGE_H_
+
+#include <fsp/soc_binding.h>
+
+void mainboard_config_gpios(void);
+void mainboard_memory_init_params(FSPM_UPD *m_upd);
+
+#endif // _MAINBOARD_FROST_CREEK_ROMSTAGE_H_
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-22 11:15:50 +0000