diff options
| -rw-r--r-- | src/mainboard/google/lars/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/google/lars/devicetree.cb | 4 |
2 files changed, 3 insertions, 2 deletions
diff --git a/src/mainboard/google/lars/Kconfig b/src/mainboard/google/lars/Kconfig index 94ec30f963..2bf25475d7 100644 --- a/src/mainboard/google/lars/Kconfig +++ b/src/mainboard/google/lars/Kconfig @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EC_GOOGLE_CHROMEEC_LPC select EC_GOOGLE_CHROMEEC_MEC select EC_GOOGLE_CHROMEEC_PD + select EXCLUDE_NATIVE_SD_INTERFACE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb index 677ee0bcc8..d85d25c61d 100644 --- a/src/mainboard/google/lars/devicetree.cb +++ b/src/mainboard/google/lars/devicetree.cb @@ -36,7 +36,7 @@ chip soc/intel/skylake register "Cio2Enable" = "0" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "2" + register "ScsSdCardEnabled" = "0" register "IshEnable" = "0" register "PttSwitch" = "0" register "InternalGfx" = "1" @@ -117,7 +117,7 @@ chip soc/intel/skylake device pci 1e.3 off end # GSPI #1 device pci 1e.4 on end # eMMC device pci 1e.5 off end # SDIO - device pci 1e.6 on end # SDCard + device pci 1e.6 off end # SDCard device pci 1f.0 on chip drivers/pc80/tpm device pnp 0c31.0 on end |