diff options
| -rw-r--r-- | src/soc/intel/alderlake/finalize.c | 9 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 1 |
2 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/finalize.c b/src/soc/intel/alderlake/finalize.c index f76e81c356..c71096de67 100644 --- a/src/soc/intel/alderlake/finalize.c +++ b/src/soc/intel/alderlake/finalize.c @@ -16,8 +16,10 @@ #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> #include <intelblocks/pmclib.h> +#include <intelblocks/systemagent.h> #include <intelblocks/tco.h> #include <intelblocks/thermal.h> +#include <intelpch/lockdown.h> #include <soc/p2sb.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> @@ -82,6 +84,12 @@ static void tbt_finalize(void) } } +static void sa_finalize(void) +{ + if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) + sa_lock_pam(); +} + static void soc_finalize(void *unused) { printk(BIOS_DEBUG, "Finalizing chipset.\n"); @@ -89,6 +97,7 @@ static void soc_finalize(void *unused) pch_finalize(); apm_control(APM_CNT_FINALIZE); tbt_finalize(); + sa_finalize(); /* Indicate finalize step with post code */ post_code(POST_OS_BOOT); diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 3accdbb408..7e1afde38b 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -406,6 +406,7 @@ static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg, s_cfg->PchLockDownBiosInterface = lockdown_by_fsp; s_cfg->PchUnlockGpioPads = !lockdown_by_fsp; s_cfg->RtcMemoryLock = lockdown_by_fsp; + s_cfg->SkipPamLock = !lockdown_by_fsp; /* coreboot will send EOP before loading payload */ s_cfg->EndOfPostMessage = EOP_DISABLE; |