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-rw-r--r--src/soc/amd/cezanne/Kconfig1
-rw-r--r--src/soc/amd/cezanne/fch.c40
-rw-r--r--src/soc/amd/cezanne/include/soc/southbridge.h15
-rw-r--r--src/soc/amd/common/block/gpp_clk/Kconfig4
-rw-r--r--src/soc/amd/common/block/gpp_clk/Makefile.mk3
-rw-r--r--src/soc/amd/common/block/gpp_clk/gpp_clk.c48
-rw-r--r--src/soc/amd/common/block/include/amdblocks/pci_clk_req.h19
-rw-r--r--src/soc/amd/mendocino/Kconfig1
-rw-r--r--src/soc/amd/mendocino/fch.c41
-rw-r--r--src/soc/amd/mendocino/include/soc/southbridge.h13
-rw-r--r--src/soc/amd/phoenix/Kconfig1
-rw-r--r--src/soc/amd/phoenix/fch.c41
-rw-r--r--src/soc/amd/phoenix/include/soc/southbridge.h13
13 files changed, 80 insertions, 160 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 4e22005d42..2ebf6bc719 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -44,6 +44,7 @@ config SOC_AMD_CEZANNE
select SOC_AMD_COMMON_BLOCK_DATA_FABRIC
select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN
select SOC_AMD_COMMON_BLOCK_EMMC
+ select SOC_AMD_COMMON_BLOCK_GPP_CLK
select SOC_AMD_COMMON_BLOCK_GRAPHICS
select SOC_AMD_COMMON_BLOCK_HAS_ESPI
select SOC_AMD_COMMON_BLOCK_I2C
diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c
index f065c8e454..1abe00dd1a 100644
--- a/src/soc/amd/cezanne/fch.c
+++ b/src/soc/amd/cezanne/fch.c
@@ -135,45 +135,7 @@ static void fch_init_acpi_ports(void)
static void gpp_clk_setup(void)
{
struct soc_amd_cezanne_config *cfg = config_of_soc();
-
- /* look-up table to be able to iterate over the PCIe clock output settings */
- const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = {
- GPP_CLK0_REQ_SHIFT,
- GPP_CLK1_REQ_SHIFT,
- GPP_CLK2_REQ_SHIFT,
- GPP_CLK3_REQ_SHIFT,
- GPP_CLK4_REQ_SHIFT,
- GPP_CLK5_REQ_SHIFT,
- GPP_CLK6_REQ_SHIFT,
- };
-
- uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL);
-
- pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0],
- ARRAY_SIZE(cfg->gpp_clk_config));
- for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) {
- gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]);
-
- /*
- * The remapping of values is done so that the default of the enum used for the
- * devicetree settings is the clock being enabled, so that a missing devicetree
- * configuration for this will result in an always active clock and not an
- * inactive PCIe clock output.
- */
- switch (cfg->gpp_clk_config[i]) {
- case GPP_CLK_REQ:
- gpp_clk_ctl |= GPP_CLK_REQ_EXT(gpp_clk_shift_lut[i]);
- break;
- case GPP_CLK_OFF:
- gpp_clk_ctl |= GPP_CLK_REQ_OFF(gpp_clk_shift_lut[i]);
- break;
- case GPP_CLK_ON:
- default:
- gpp_clk_ctl |= GPP_CLK_REQ_ON(gpp_clk_shift_lut[i]);
- }
- }
-
- misc_write32(GPP_CLK_CNTRL, gpp_clk_ctl);
+ gpp_clk_setup_common(&cfg->gpp_clk_config[0], ARRAY_SIZE(cfg->gpp_clk_config));
}
static void cgpll_clock_gate_init(void)
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h
index 4cd53cb5d1..bdd6644dcc 100644
--- a/src/soc/amd/cezanne/include/soc/southbridge.h
+++ b/src/soc/amd/cezanne/include/soc/southbridge.h
@@ -85,21 +85,6 @@
#define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */
-/* FCH MISC Registers 0xfed80e00 */
-#define GPP_CLK_CNTRL 0x00
-#define GPP_CLK0_REQ_SHIFT 0
-#define GPP_CLK1_REQ_SHIFT 2
-#define GPP_CLK4_REQ_SHIFT 4
-#define GPP_CLK2_REQ_SHIFT 6
-#define GPP_CLK3_REQ_SHIFT 8
-#define GPP_CLK5_REQ_SHIFT 10
-#define GPP_CLK6_REQ_SHIFT 12
-#define GPP_CLK_OUTPUT_COUNT 7
-#define GPP_CLK_REQ_MASK(clk_shift) (0x3 << (clk_shift))
-#define GPP_CLK_REQ_ON(clk_shift) (0x3 << (clk_shift))
-#define GPP_CLK_REQ_EXT(clk_shift) (0x1 << (clk_shift))
-#define GPP_CLK_REQ_OFF(clk_shift) (0x0 << (clk_shift))
-
#define MISC_CLKGATEDCNTL 0x2c
#define ALINKCLK_GATEOFFEN BIT(16)
#define BLINKCLK_GATEOFFEN BIT(17)
diff --git a/src/soc/amd/common/block/gpp_clk/Kconfig b/src/soc/amd/common/block/gpp_clk/Kconfig
new file mode 100644
index 0000000000..0838df41d4
--- /dev/null
+++ b/src/soc/amd/common/block/gpp_clk/Kconfig
@@ -0,0 +1,4 @@
+config SOC_AMD_COMMON_BLOCK_GPP_CLK
+ bool
+ help
+ Select this option to use AMD common PCIe clk generator configuration.
diff --git a/src/soc/amd/common/block/gpp_clk/Makefile.mk b/src/soc/amd/common/block/gpp_clk/Makefile.mk
new file mode 100644
index 0000000000..4b943f4908
--- /dev/null
+++ b/src/soc/amd/common/block/gpp_clk/Makefile.mk
@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_GPP_CLK) += gpp_clk.c
diff --git a/src/soc/amd/common/block/gpp_clk/gpp_clk.c b/src/soc/amd/common/block/gpp_clk/gpp_clk.c
new file mode 100644
index 0000000000..20d768ffac
--- /dev/null
+++ b/src/soc/amd/common/block/gpp_clk/gpp_clk.c
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/acpimmio.h>
+#include <amdblocks/pci_clk_req.h>
+#include <types.h>
+
+/* configure the general purpose PCIe clock outputs according to the devicetree settings */
+void gpp_clk_setup_common(enum gpp_clk_req *gpp_clk_config, size_t gpp_clk_config_num)
+{
+ /* look-up table to be able to iterate over the PCIe clock output settings */
+ const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = {
+ GPP_CLK0_REQ_SHIFT,
+ GPP_CLK1_REQ_SHIFT,
+ GPP_CLK2_REQ_SHIFT,
+ GPP_CLK3_REQ_SHIFT,
+ GPP_CLK4_REQ_SHIFT,
+ GPP_CLK5_REQ_SHIFT,
+ GPP_CLK6_REQ_SHIFT,
+ };
+
+ uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL);
+
+ pcie_gpp_dxio_update_clk_req_config(gpp_clk_config, gpp_clk_config_num);
+ for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) {
+ gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]);
+ /*
+ * The remapping of values is done so that the default of the enum used for the
+ * devicetree settings is the clock being enabled, so that a missing devicetree
+ * configuration for this will result in an always active clock and not an
+ * inactive PCIe clock output. Only the configuration for the clock outputs
+ * available on the package is provided via the devicetree; the rest is
+ * switched off unconditionally.
+ */
+ switch (i < gpp_clk_config_num ? gpp_clk_config[i] : GPP_CLK_OFF) {
+ case GPP_CLK_REQ:
+ gpp_clk_ctl |= GPP_CLK_REQ_EXT(gpp_clk_shift_lut[i]);
+ break;
+ case GPP_CLK_OFF:
+ gpp_clk_ctl |= GPP_CLK_REQ_OFF(gpp_clk_shift_lut[i]);
+ break;
+ case GPP_CLK_ON:
+ default:
+ gpp_clk_ctl |= GPP_CLK_REQ_ON(gpp_clk_shift_lut[i]);
+ }
+ }
+
+ misc_write32(GPP_CLK_CNTRL, gpp_clk_ctl);
+}
diff --git a/src/soc/amd/common/block/include/amdblocks/pci_clk_req.h b/src/soc/amd/common/block/include/amdblocks/pci_clk_req.h
index 7c10e5d604..811fe68d10 100644
--- a/src/soc/amd/common/block/include/amdblocks/pci_clk_req.h
+++ b/src/soc/amd/common/block/include/amdblocks/pci_clk_req.h
@@ -5,6 +5,21 @@
#include <types.h>
+/* FCH MISC Registers 0xfed80e00 */
+#define GPP_CLK_CNTRL 0x00
+#define GPP_CLK0_REQ_SHIFT 0
+#define GPP_CLK1_REQ_SHIFT 2
+#define GPP_CLK4_REQ_SHIFT 4
+#define GPP_CLK2_REQ_SHIFT 6
+#define GPP_CLK3_REQ_SHIFT 8
+#define GPP_CLK5_REQ_SHIFT 10
+#define GPP_CLK6_REQ_SHIFT 12
+#define GPP_CLK_OUTPUT_COUNT 7
+#define GPP_CLK_REQ_MASK(clk_shift) (0x3 << (clk_shift))
+#define GPP_CLK_REQ_ON(clk_shift) (0x3 << (clk_shift))
+#define GPP_CLK_REQ_EXT(clk_shift) (0x1 << (clk_shift))
+#define GPP_CLK_REQ_OFF(clk_shift) (0x0 << (clk_shift))
+
enum gpp_clk_req {
GPP_CLK_ON, /* GPP clock always on; default */
GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */
@@ -14,4 +29,8 @@ enum gpp_clk_req {
void pcie_gpp_dxio_update_clk_req_config(enum gpp_clk_req *gpp_clk_config,
size_t gpp_clk_config_num);
+/* configure the general purpose PCIe clock outputs according to the devicetree settings */
+void gpp_clk_setup_common(enum gpp_clk_req *gpp_clk_config,
+ size_t gpp_clk_config_num);
+
#endif
diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig
index 7f613387cd..f6305ee5e9 100644
--- a/src/soc/amd/mendocino/Kconfig
+++ b/src/soc/amd/mendocino/Kconfig
@@ -48,6 +48,7 @@ config SOC_AMD_REMBRANDT_BASE
select SOC_AMD_COMMON_BLOCK_DATA_FABRIC
select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN
select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES
+ select SOC_AMD_COMMON_BLOCK_GPP_CLK
select SOC_AMD_COMMON_BLOCK_GRAPHICS
select SOC_AMD_COMMON_BLOCK_HAS_ESPI
select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE
diff --git a/src/soc/amd/mendocino/fch.c b/src/soc/amd/mendocino/fch.c
index 772cca0600..8fb0190396 100644
--- a/src/soc/amd/mendocino/fch.c
+++ b/src/soc/amd/mendocino/fch.c
@@ -130,46 +130,7 @@ static void fch_init_acpi_ports(void)
static void gpp_clk_setup(void)
{
struct soc_amd_mendocino_config *cfg = config_of_soc();
-
- /* look-up table to be able to iterate over the PCIe clock output settings */
- const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = {
- GPP_CLK0_REQ_SHIFT,
- GPP_CLK1_REQ_SHIFT,
- GPP_CLK2_REQ_SHIFT,
- GPP_CLK3_REQ_SHIFT,
- GPP_CLK4_REQ_SHIFT,
- GPP_CLK5_REQ_SHIFT,
- GPP_CLK6_REQ_SHIFT,
- };
-
- uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL);
-
- pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0],
- ARRAY_SIZE(cfg->gpp_clk_config));
- for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) {
- gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]);
- /*
- * The remapping of values is done so that the default of the enum used for the
- * devicetree settings is the clock being enabled, so that a missing devicetree
- * configuration for this will result in an always active clock and not an
- * inactive PCIe clock output. Only the configuration for the clock outputs
- * available on the package is provided via the devicetree; the rest is
- * switched off unconditionally.
- */
- switch (i < GPP_CLK_OUTPUT_AVAILABLE ? cfg->gpp_clk_config[i] : GPP_CLK_OFF) {
- case GPP_CLK_REQ:
- gpp_clk_ctl |= GPP_CLK_REQ_EXT(gpp_clk_shift_lut[i]);
- break;
- case GPP_CLK_OFF:
- gpp_clk_ctl |= GPP_CLK_REQ_OFF(gpp_clk_shift_lut[i]);
- break;
- case GPP_CLK_ON:
- default:
- gpp_clk_ctl |= GPP_CLK_REQ_ON(gpp_clk_shift_lut[i]);
- }
- }
-
- misc_write32(GPP_CLK_CNTRL, gpp_clk_ctl);
+ gpp_clk_setup_common(&cfg->gpp_clk_config[0], ARRAY_SIZE(cfg->gpp_clk_config));
}
static void cgpll_clock_gate_init(void)
diff --git a/src/soc/amd/mendocino/include/soc/southbridge.h b/src/soc/amd/mendocino/include/soc/southbridge.h
index 2e88c77329..9b276d2636 100644
--- a/src/soc/amd/mendocino/include/soc/southbridge.h
+++ b/src/soc/amd/mendocino/include/soc/southbridge.h
@@ -85,20 +85,7 @@
#define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */
/* FCH MISC Registers 0xfed80e00 */
-#define GPP_CLK_CNTRL 0x00
-#define GPP_CLK0_REQ_SHIFT 0
-#define GPP_CLK1_REQ_SHIFT 2
-#define GPP_CLK4_REQ_SHIFT 4
-#define GPP_CLK2_REQ_SHIFT 6
-#define GPP_CLK3_REQ_SHIFT 8
-#define GPP_CLK5_REQ_SHIFT 10
-#define GPP_CLK6_REQ_SHIFT 12
-#define GPP_CLK_OUTPUT_COUNT 7
#define GPP_CLK_OUTPUT_AVAILABLE 4
-#define GPP_CLK_REQ_MASK(clk_shift) (0x3 << (clk_shift))
-#define GPP_CLK_REQ_ON(clk_shift) (0x3 << (clk_shift))
-#define GPP_CLK_REQ_EXT(clk_shift) (0x1 << (clk_shift))
-#define GPP_CLK_REQ_OFF(clk_shift) (0x0 << (clk_shift))
#define MISC_CLKGATEDCNTL 0x2c
#define ALINKCLK_GATEOFFEN BIT(16)
diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig
index 0acf62ba92..9d45b76203 100644
--- a/src/soc/amd/phoenix/Kconfig
+++ b/src/soc/amd/phoenix/Kconfig
@@ -43,6 +43,7 @@ config SOC_AMD_PHOENIX_BASE
select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN
select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT
select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES
+ select SOC_AMD_COMMON_BLOCK_GPP_CLK
select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct
select SOC_AMD_COMMON_BLOCK_HAS_ESPI
select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE
diff --git a/src/soc/amd/phoenix/fch.c b/src/soc/amd/phoenix/fch.c
index 1e03cda105..779d448682 100644
--- a/src/soc/amd/phoenix/fch.c
+++ b/src/soc/amd/phoenix/fch.c
@@ -128,46 +128,7 @@ static void fch_init_acpi_ports(void)
static void gpp_clk_setup(void)
{
struct soc_amd_phoenix_config *cfg = config_of_soc();
-
- /* look-up table to be able to iterate over the PCIe clock output settings */
- const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = {
- GPP_CLK0_REQ_SHIFT,
- GPP_CLK1_REQ_SHIFT,
- GPP_CLK2_REQ_SHIFT,
- GPP_CLK3_REQ_SHIFT,
- GPP_CLK4_REQ_SHIFT,
- GPP_CLK5_REQ_SHIFT,
- GPP_CLK6_REQ_SHIFT,
- };
-
- uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL);
-
- pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0],
- ARRAY_SIZE(cfg->gpp_clk_config));
- for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) {
- gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]);
- /*
- * The remapping of values is done so that the default of the enum used for the
- * devicetree settings is the clock being enabled, so that a missing devicetree
- * configuration for this will result in an always active clock and not an
- * inactive PCIe clock output. Only the configuration for the clock outputs
- * available on the package is provided via the devicetree; the rest is
- * switched off unconditionally.
- */
- switch (i < GPP_CLK_OUTPUT_AVAILABLE ? cfg->gpp_clk_config[i] : GPP_CLK_OFF) {
- case GPP_CLK_REQ:
- gpp_clk_ctl |= GPP_CLK_REQ_EXT(gpp_clk_shift_lut[i]);
- break;
- case GPP_CLK_OFF:
- gpp_clk_ctl |= GPP_CLK_REQ_OFF(gpp_clk_shift_lut[i]);
- break;
- case GPP_CLK_ON:
- default:
- gpp_clk_ctl |= GPP_CLK_REQ_ON(gpp_clk_shift_lut[i]);
- }
- }
-
- misc_write32(GPP_CLK_CNTRL, gpp_clk_ctl);
+ gpp_clk_setup_common(&cfg->gpp_clk_config[0], ARRAY_SIZE(cfg->gpp_clk_config));
}
static void cgpll_clock_gate_init(void)
diff --git a/src/soc/amd/phoenix/include/soc/southbridge.h b/src/soc/amd/phoenix/include/soc/southbridge.h
index 9b84934258..db0e30440d 100644
--- a/src/soc/amd/phoenix/include/soc/southbridge.h
+++ b/src/soc/amd/phoenix/include/soc/southbridge.h
@@ -84,20 +84,7 @@
#define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */
/* FCH MISC Registers 0xfed80e00 */
-#define GPP_CLK_CNTRL 0x00
-#define GPP_CLK0_REQ_SHIFT 0
-#define GPP_CLK1_REQ_SHIFT 2
-#define GPP_CLK4_REQ_SHIFT 4
-#define GPP_CLK2_REQ_SHIFT 6
-#define GPP_CLK3_REQ_SHIFT 8
-#define GPP_CLK5_REQ_SHIFT 10
-#define GPP_CLK6_REQ_SHIFT 12
-#define GPP_CLK_OUTPUT_COUNT 7
#define GPP_CLK_OUTPUT_AVAILABLE 7
-#define GPP_CLK_REQ_MASK(clk_shift) (0x3 << (clk_shift))
-#define GPP_CLK_REQ_ON(clk_shift) (0x3 << (clk_shift))
-#define GPP_CLK_REQ_EXT(clk_shift) (0x1 << (clk_shift))
-#define GPP_CLK_REQ_OFF(clk_shift) (0x0 << (clk_shift))
#define MISC_CLKGATEDCNTL 0x2c
#define ALINKCLK_GATEOFFEN BIT(16)
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-19 17:24:28 +0000