diff options
| -rw-r--r-- | src/cpu/amd/model_10xxx/fidvid.c | 20 | ||||
| -rw-r--r-- | src/northbridge/amd/amdht/AsPsDefs.h | 2 |
2 files changed, 22 insertions, 0 deletions
diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c index bfa03446d2..53a5f18751 100644 --- a/src/cpu/amd/model_10xxx/fidvid.c +++ b/src/cpu/amd/model_10xxx/fidvid.c @@ -65,6 +65,25 @@ static void enable_fid_change(u8 fid) dword); } } +static void enableNbPState1( device_t dev ) { + u32 cpuRev = mctGetLogicalCPUID(0xFF); + if (cpuRev & AMD_FAM10_C3) { + u32 nbPState = (pci_read_config32(dev, 0x1F0) & NB_PSTATE_MASK); + if ( nbPState){ + u32 nbVid1 = (pci_read_config32(dev, 0x1F4) & NB_VID1_MASK) >> NB_VID1_SHIFT; + u32 i; + for (i = nbPState; i < NM_PS_REG; i++) { + msr_t msr = rdmsr(PS_REG_BASE + i); + if (msr.hi & PS_EN_MASK ) { + msr.hi |= NB_DID_M_ON; + msr.lo &= NB_VID_MASK_OFF; + msr.lo |= ( nbVid1 << NB_VID_POS); + wrmsr(PS_REG_BASE + i, msr); + } + } + } + } +} static void setVSRamp(device_t dev) { /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSRampTime] @@ -800,6 +819,7 @@ static void init_fidvid_stage2(u32 apicid, u32 nodeid) dtemp |= PLLLOCK_DFT_L; pci_write_config32(dev, 0xA0, dtemp); + enableNbPState1(dev); finalPstateChange(); /* Set TSC to tick at the P0 ndfid rate */ diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h index 07f46631b2..13e6548873 100644 --- a/src/northbridge/amd/amdht/AsPsDefs.h +++ b/src/northbridge/amd/amdht/AsPsDefs.h @@ -153,6 +153,8 @@ #define PS_2 0x00020000 /* P-state 2 */ #define PS_CPU_DID_1 0x40 /* Cpu Did 1 */ +#define NB_VID1_MASK 0x00003f80 /* F3x1F4[NbVid1]*/ +#define NB_VID1_SHIFT 7 /* F3x1F4[NbVid1] */ |