diff options
| -rw-r--r-- | src/mainboard/google/rambi/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/chip.h | 11 |
2 files changed, 0 insertions, 13 deletions
diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index 5d9eec535e..5587006f88 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -40,14 +40,12 @@ chip soc/intel/baytrail register "pcie_wake_enable" = "1" # Enable PIPEA as DP_C - register "gpu_pipea_hotplug" = "6" # 6ms Pulse register "gpu_pipea_port_select" = "2" # DP_C register "gpu_pipea_power_cycle_delay" = "5" # 400ms register "gpu_pipea_power_on_delay" = "2000" # 200ms register "gpu_pipea_light_on_delay" = "10" # 1ms register "gpu_pipea_power_off_delay" = "500" # 50ms register "gpu_pipea_light_off_delay" = "2000" # 200ms - register "gpu_pipea_backlight_pwm" = "0x400" # VR PS2 control register "vnn_ps2_enable" = "1" diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h index 256ed4f2fa..0860a9666a 100644 --- a/src/soc/intel/baytrail/chip.h +++ b/src/soc/intel/baytrail/chip.h @@ -72,30 +72,19 @@ struct soc_intel_baytrail_config { /* Allow PCIe devices to wake system from suspend. */ int pcie_wake_enable; - /* - * Digital Port Hotplug Enable: - * 0x04 = Enabled, 2ms short pulse - * 0x05 = Enabled, 4.5ms short pulse - * 0x06 = Enabled, 6ms short pulse - * 0x07 = Enabled, 100ms short pulse - */ - int gpu_pipea_hotplug; int gpu_pipea_port_select; /* Port select: 1=DP_B 2=DP_C */ uint16_t gpu_pipea_power_on_delay; uint16_t gpu_pipea_light_on_delay; uint16_t gpu_pipea_power_off_delay; uint16_t gpu_pipea_light_off_delay; uint16_t gpu_pipea_power_cycle_delay; - uint32_t gpu_pipea_backlight_pwm; - int gpu_pipeb_hotplug; int gpu_pipeb_port_select; /* Port select: 1=DP_B 2=DP_C */ uint16_t gpu_pipeb_power_on_delay; uint16_t gpu_pipeb_light_on_delay; uint16_t gpu_pipeb_power_off_delay; uint16_t gpu_pipeb_light_off_delay; uint16_t gpu_pipeb_power_cycle_delay; - uint32_t gpu_pipeb_backlight_pwm; }; extern struct chip_operations soc_intel_baytrail_ops; |