4 files changed, 20 insertions, 20 deletions
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 70ba301c38..da1c7e4d6e 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -115,7 +115,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
 }
 
 #ifndef __SMM__
-static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset)
+static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)
 {
 	u32 dword = pci_read_config32(dev, offset);
 	memcpy(ptr, &dword, sizeof(dword));
@@ -543,7 +543,7 @@ void intel_me_finalize_smm(void)
 #else /* !__SMM__ */
 
 /* Determine the path that we should take based on ME status */
-static me_bios_path intel_me_path(device_t dev)
+static me_bios_path intel_me_path(struct device *dev)
 {
 	me_bios_path path = ME_DISABLE_BIOS_PATH;
 	struct me_hfs hfs;
@@ -610,7 +610,7 @@ static me_bios_path intel_me_path(device_t dev)
 }
 
 /* Prepare ME for MEI messages */
-static int intel_mei_setup(device_t dev)
+static int intel_mei_setup(struct device *dev)
 {
 	struct resource *res;
 	struct mei_csr host;
@@ -640,7 +640,7 @@ static int intel_mei_setup(device_t dev)
 }
 
 /* Read the Extend register hash of ME firmware */
-static int intel_me_extend_valid(device_t dev)
+static int intel_me_extend_valid(struct device *dev)
 {
 	struct me_heres status;
 	u32 extend[8] = {0};
@@ -687,14 +687,14 @@ static int intel_me_extend_valid(device_t dev)
 }
 
 /* Hide the ME virtual PCI devices */
-static void intel_me_hide(device_t dev)
+static void intel_me_hide(struct device *dev)
 {
 	dev->enabled = 0;
 	pch_enable(dev);
 }
 
 /* Check whether ME is present and do basic init */
-static void intel_me_init(device_t dev)
+static void intel_me_init(struct device *dev)
 {
 	me_bios_path path = intel_me_path(dev);
 
@@ -736,7 +736,7 @@ static void intel_me_init(device_t dev)
 	}
 }
 
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
 {
 	if (!vendor || !device) {
 		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index 90117870e4..1a59dc4024 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -117,7 +117,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
 }
 
 #ifndef __SMM__
-static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset)
+static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)
 {
 	u32 dword = pci_read_config32(dev, offset);
 	memcpy(ptr, &dword, sizeof(dword));
@@ -523,7 +523,7 @@ void intel_me8_finalize_smm(void)
 #else /* !__SMM__ */
 
 /* Determine the path that we should take based on ME status */
-static me_bios_path intel_me_path(device_t dev)
+static me_bios_path intel_me_path(struct device *dev)
 {
 	me_bios_path path = ME_DISABLE_BIOS_PATH;
 	struct me_hfs hfs;
@@ -597,7 +597,7 @@ static me_bios_path intel_me_path(device_t dev)
 }
 
 /* Prepare ME for MEI messages */
-static int intel_mei_setup(device_t dev)
+static int intel_mei_setup(struct device *dev)
 {
 	struct resource *res;
 	struct mei_csr host;
@@ -627,7 +627,7 @@ static int intel_mei_setup(device_t dev)
 }
 
 /* Read the Extend register hash of ME firmware */
-static int intel_me_extend_valid(device_t dev)
+static int intel_me_extend_valid(struct device *dev)
 {
 	struct me_heres status;
 	u32 extend[8] = {0};
@@ -674,14 +674,14 @@ static int intel_me_extend_valid(device_t dev)
 }
 
 /* Hide the ME virtual PCI devices */
-static void intel_me_hide(device_t dev)
+static void intel_me_hide(struct device *dev)
 {
 	dev->enabled = 0;
 	pch_enable(dev);
 }
 
 /* Check whether ME is present and do basic init */
-static void intel_me_init(device_t dev)
+static void intel_me_init(struct device *dev)
 {
 	me_bios_path path = intel_me_path(dev);
 	me_bios_payload mbp_data;
@@ -739,7 +739,7 @@ static void intel_me_init(device_t dev)
 	}
 }
 
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
 {
 	if (!vendor || !device) {
 		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c
index 79cf6bf382..00265d0219 100644
--- a/src/southbridge/intel/bd82x6x/pch.c
+++ b/src/southbridge/intel/bd82x6x/pch.c
@@ -208,9 +208,9 @@ static void pch_hide_devfn(unsigned devfn)
 }
 
 /* Check if any port in set X to X+3 is enabled */
-static int pch_pcie_check_set_enabled(device_t dev)
+static int pch_pcie_check_set_enabled(struct device *dev)
 {
-	device_t port;
+	struct device *port;
 	int port_func;
 	int dev_func = PCI_FUNC(dev->path.pci.devfn);
 
@@ -258,7 +258,7 @@ static void pch_pcie_function_swap(u8 old_fn, u8 new_fn)
 static void pch_pcie_devicetree_update(
 		struct southbridge_intel_bd82x6x_config *config)
 {
-	device_t dev;
+	struct device *dev;
 
 	/*
 	 * hotplug map should also be updated along with their
@@ -312,7 +312,7 @@ static void pch_pcie_devicetree_update(
 }
 
 /* Special handling for PCIe Root Port devices */
-static void pch_pcie_enable(device_t dev)
+static void pch_pcie_enable(struct device *dev)
 {
 	struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
 	u32 reg32;
@@ -422,7 +422,7 @@ static void pch_pcie_enable(device_t dev)
 	}
 }
 
-void pch_enable(device_t dev)
+void pch_enable(struct device *dev)
 {
 	u32 reg32;
 
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 65aac55b29..66f5727e61 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -64,7 +64,7 @@ void intel_pch_finalize_smm(void);
 #if !defined(__PRE_RAM__)
 #if !defined(__SIMPLE_DEVICE__)
 #include "chip.h"
-void pch_enable(device_t dev);
+void pch_enable(struct device *dev);
 #endif
 int pch_silicon_revision(void);
 int pch_silicon_type(void);