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-rw-r--r--src/mainboard/google/asurada/Makefile.inc3
-rw-r--r--src/mainboard/google/asurada/bootblock.c4
-rw-r--r--src/mainboard/google/asurada/chromeos.c23
-rw-r--r--src/mainboard/google/asurada/gpio.h20
4 files changed, 48 insertions, 2 deletions
diff --git a/src/mainboard/google/asurada/Makefile.inc b/src/mainboard/google/asurada/Makefile.inc
index c74253994c..02fb8300e0 100644
--- a/src/mainboard/google/asurada/Makefile.inc
+++ b/src/mainboard/google/asurada/Makefile.inc
@@ -2,12 +2,15 @@ subdirs-y += sdram_params/
bootblock-y += memlayout.ld
bootblock-y += bootblock.c
+bootblock-y += chromeos.c
verstage-y += memlayout.ld
+verstage-y += chromeos.c
verstage-y += reset.c
romstage-y += memlayout.ld
romstage-y += boardid.c
+romstage-y += chromeos.c
romstage-y += romstage.c
romstage-y += sdram_configs.c
diff --git a/src/mainboard/google/asurada/bootblock.c b/src/mainboard/google/asurada/bootblock.c
index cce14381f6..04e8898d85 100644
--- a/src/mainboard/google/asurada/bootblock.c
+++ b/src/mainboard/google/asurada/bootblock.c
@@ -3,8 +3,12 @@
#include <bootblock_common.h>
#include <soc/spi.h>
+#include "gpio.h"
+
void bootblock_mainboard_init(void)
{
mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0);
mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0);
+ setup_chromeos_gpios();
+ gpio_eint_configure(GPIO_H1_AP_INT, IRQ_TYPE_EDGE_RISING);
}
diff --git a/src/mainboard/google/asurada/chromeos.c b/src/mainboard/google/asurada/chromeos.c
index 8f9fa5334c..a57392bc04 100644
--- a/src/mainboard/google/asurada/chromeos.c
+++ b/src/mainboard/google/asurada/chromeos.c
@@ -5,16 +5,35 @@
#include <gpio.h>
#include <security/tpm/tis.h>
+#include "gpio.h"
+
+void setup_chromeos_gpios(void)
+{
+ gpio_input(GPIO_WP);
+ gpio_input_pullup(GPIO_EC_AP_INT);
+ gpio_input_pullup(GPIO_EC_IN_RW);
+ gpio_input_pullup(GPIO_H1_AP_INT);
+ gpio_input_pullup(GPIO_SD_CD);
+ gpio_output(GPIO_RESET, 0);
+}
+
void fill_lb_gpios(struct lb_gpios *gpios)
{
+ struct lb_gpio chromeos_gpios[] = {
+ {GPIO_EC_IN_RW.id, ACTIVE_LOW, -1, "EC in RW"},
+ {GPIO_EC_AP_INT.id, ACTIVE_LOW, -1, "EC interrupt"},
+ {GPIO_H1_AP_INT.id, ACTIVE_HIGH, -1, "TPM interrupt"},
+ {GPIO_SD_CD.id, ACTIVE_HIGH, -1, "SD card detect"},
+ };
+ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
}
int get_write_protect_state(void)
{
- return 0;
+ return !gpio_get(GPIO_WP);
}
int tis_plat_irq_status(void)
{
- return 0;
+ return gpio_eint_poll(GPIO_H1_AP_INT);
}
diff --git a/src/mainboard/google/asurada/gpio.h b/src/mainboard/google/asurada/gpio.h
new file mode 100644
index 0000000000..90de583f77
--- /dev/null
+++ b/src/mainboard/google/asurada/gpio.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __MAINBOARD_GOOGLE_ASURADA_GPIO_H__
+#define __MAINBOARD_GOOGLE_ASURADA_GPIO_H__
+
+#include <soc/gpio.h>
+
+/* AP_FLASH_WP */
+#define GPIO_WP GPIO(EINT14)
+#define GPIO_EC_AP_INT GPIO(EINT5)
+#define GPIO_EC_IN_RW GPIO(ANT_SEL8)
+#define GPIO_H1_AP_INT GPIO(ANT_SEL9)
+/* SD Card Detection */
+#define GPIO_SD_CD GPIO(EINT17)
+/* AP_EC_WARM_RST_REQ */
+#define GPIO_RESET GPIO(CAM_PDN2)
+
+void setup_chromeos_gpios(void);
+
+#endif