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-rw-r--r--src/southbridge/intel/bd82x6x/finalize.c4
-rw-r--r--src/southbridge/intel/bd82x6x/pch.h1
2 files changed, 3 insertions, 2 deletions
diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c
index c9296fd949..4e08fc68d3 100644
--- a/src/southbridge/intel/bd82x6x/finalize.c
+++ b/src/southbridge/intel/bd82x6x/finalize.c
@@ -60,10 +60,10 @@ void intel_pch_finalize_smm(void)
RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7));
/* Global SMI Lock */
- pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4);
+ pci_or_config16(PCH_LPC_DEV, GEN_PMCON_1, 1 << 4);
/* GEN_PMCON Lock */
- pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2));
+ pci_or_config8(PCH_LPC_DEV, GEN_PMCON_LOCK, (1 << 1) | (1 << 2));
/* R/WO registers */
RCBA32(0x21a4) = RCBA32(0x21a4);
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 8b22fca334..da1f901f5e 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -140,6 +140,7 @@ early_usb_init (const struct southbridge_usb_port *portmap);
#define GEN_PMCON_1 0xa0
#define GEN_PMCON_2 0xa2
#define GEN_PMCON_3 0xa4
+#define GEN_PMCON_LOCK 0xa6
#define ETR3 0xac
#define ETR3_CWORWRE (1 << 18)
#define ETR3_CF9GR (1 << 20)