diff options
| -rw-r--r-- | src/devices/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/devices/cpu_device.c | 71 | ||||
| -rw-r--r-- | src/include/device/device.h | 10 | ||||
| -rw-r--r-- | src/include/device/path.h | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/agesa/family10/northbridge.c | 23 | ||||
| -rw-r--r-- | src/northbridge/amd/agesa/family14/northbridge.c | 17 | ||||
| -rw-r--r-- | src/northbridge/amd/agesa/family15/northbridge.c | 26 | ||||
| -rw-r--r-- | src/northbridge/amd/agesa/family15tn/northbridge.c | 26 | ||||
| -rw-r--r-- | src/northbridge/amd/amdfam10/northbridge.c | 32 | ||||
| -rw-r--r-- | src/northbridge/amd/amdk8/northbridge.c | 36 |
10 files changed, 124 insertions, 120 deletions
diff --git a/src/devices/Makefile.inc b/src/devices/Makefile.inc index 9a2f71e683..9d4b39146c 100644 --- a/src/devices/Makefile.inc +++ b/src/devices/Makefile.inc @@ -1,5 +1,6 @@ ramstage-y += device.c ramstage-y += root_device.c +ramstage-y += cpu_device.c ramstage-y += device_util.c ramstage-y += pci_device.c ramstage-$(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) += hypertransport.c diff --git a/src/devices/cpu_device.c b/src/devices/cpu_device.c new file mode 100644 index 0000000000..b689f1abb3 --- /dev/null +++ b/src/devices/cpu_device.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <console/console.h> +#include <cpu/x86/lapic.h> + +void remap_bsp_lapic(struct bus *cpu_bus) +{ + struct device_path cpu_path; + device_t cpu; + u32 bsp_lapic_id = lapicid(); + + if (bsp_lapic_id) { + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = 0; + cpu = find_dev_path(cpu_bus, &cpu_path); + if (cpu) + cpu->path.apic.apic_id = bsp_lapic_id; + } +} + +device_t add_cpu_device(struct bus *cpu_bus, unsigned apic_id, int enabled) +{ + struct device_path cpu_path; + device_t cpu; + + /* Build the cpu device path */ + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = apic_id; + + /* Update CPU in devicetree. */ + if (enabled) + cpu = alloc_find_dev(cpu_bus, &cpu_path); + else + cpu = find_dev_path(cpu_bus, &cpu_path); + if (!cpu) + return NULL; + + cpu->enabled = enabled; + printk(BIOS_DEBUG, "CPU: %s %s\n", + dev_path(cpu), cpu->enabled?"enabled":"disabled"); + + return cpu; +} + +void set_cpu_topology(device_t cpu, unsigned node, unsigned package, unsigned core, unsigned thread) +{ + cpu->path.apic.node_id = node; + cpu->path.apic.package_id = package; + cpu->path.apic.core_id = core; + cpu->path.apic.thread_id = thread; +} + diff --git a/src/include/device/device.h b/src/include/device/device.h index 772b737cd9..642a4a6358 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -155,6 +155,16 @@ device_t dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); device_t dev_find_lapic(unsigned apic_id); int dev_count_cpu(void); +void remap_bsp_lapic(struct bus *cpu_bus); +device_t add_cpu_device(struct bus *cpu_bus, unsigned apic_id, int enabled); +void set_cpu_topology(device_t cpu, unsigned node, unsigned package, unsigned core, unsigned thread); + +#define amd_cpu_topology(cpu, node, core) \ + set_cpu_topology(cpu, node, 0, core, 0) + +#define intel_cpu_topology(cpu, package, core, thread) \ + set_cpu_topology(cpu, 0, package, core, thread) + /* Debug functions */ void print_resource_tree(struct device * root, int debug_level, const char *msg); diff --git a/src/include/device/path.h b/src/include/device/path.h index 5af761e80b..16ad8f9089 100644 --- a/src/include/device/path.h +++ b/src/include/device/path.h @@ -39,8 +39,10 @@ struct i2c_path struct apic_path { unsigned apic_id; + unsigned package_id; unsigned node_id; unsigned core_id; + unsigned thread_id; }; struct ioapic_path diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 3a3580a66a..01240761ca 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -1374,11 +1374,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; u32 modules = TopologyConfiguration.PlatformNumberOfModules; u32 lapicid_start = 0; - struct device_path cpu_path; - device_t cpu; - /* Build the cpu device path */ - cpu_path.type = DEVICE_PATH_APIC; /* * APIC ID calucation is tightly coupled with AGESA v5 code. * This calculation MUST match the assignment calculation done @@ -1394,22 +1390,11 @@ static u32 cpu_bus_scan(device_t dev, u32 max) if (nodes * (cores_found + 1) >= 0x10) { lapicid_start = 0x10; } - cpu_path.apic.apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (cores_found + 1)) : j); - - /* Update CPU in devicetree. */ - if (enable_node) - cpu = alloc_find_dev(cpu_bus, &cpu_path); - else - cpu = find_dev_path(cpu_bus, &cpu_path); - if (!cpu) - continue; - - cpu->enabled = enable_node; - cpu->path.apic.node_id = i; - cpu->path.apic.core_id = j; - printk(BIOS_DEBUG, "CPU: %s %s\n", - dev_path(cpu), cpu->enabled?"enabled":"disabled"); + u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (cores_found + 1)) : j); + device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + if (cpu) + amd_cpu_topology(cpu, i, j); } //j } return max; diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 2d0a85f7b4..8742f11904 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -831,6 +831,7 @@ static void cpu_bus_set_resources(device_t dev) { static u32 cpu_bus_scan(device_t dev, u32 max) { + struct bus *cpu_bus = dev->link_list; device_t cpu; int apic_id, cores_found; @@ -842,20 +843,10 @@ static u32 cpu_bus_scan(device_t dev, u32 max) cores_found = (pci_read_config32(dev_find_slot(0,PCI_DEVFN(0x18,0x3)), 0xe8) >> 12) & 3; printk(BIOS_DEBUG, " AP siblings=%d\n", cores_found); - for (apic_id = 0; apic_id <= cores_found; apic_id++) { - struct device_path cpu_path; - - cpu_path.type = DEVICE_PATH_APIC; - cpu_path.apic.apic_id = apic_id; - cpu = alloc_find_dev(dev->link_list, &cpu_path); - if (!cpu) - continue; - cpu->enabled = 1; - cpu->path.apic.node_id = 0; - cpu->path.apic.core_id = apic_id; - printk(BIOS_DEBUG, "CPU: %s %s\n", - dev_path(cpu), cpu->enabled?"enabled":"disabled"); + cpu = add_cpu_device(cpu_bus, apic_id, 1); + if (cpu) + amd_cpu_topology(cpu, 0, apic_id); } return max; } diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 02270e7e12..742ef890cf 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -1052,11 +1052,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; u32 modules = TopologyConfiguration.PlatformNumberOfModules; u32 lapicid_start = 0; - struct device_path cpu_path; - device_t cpu; - /* Build the cpu device path */ - cpu_path.type = DEVICE_PATH_APIC; /* * APIC ID calucation is tightly coupled with AGESA v5 code. * This calculation MUST match the assignment calculation done @@ -1078,23 +1074,13 @@ static u32 cpu_bus_scan(device_t dev, u32 max) lapicid_start = (lapicid_start + 1) * core_max; printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); } - cpu_path.apic.apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); + u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", - i, j, cpu_path.apic.apic_id); - - /* Update CPU in devicetree. */ - if (enable_node) - cpu = alloc_find_dev(cpu_bus, &cpu_path); - else - cpu = find_dev_path(cpu_bus, &cpu_path); - if (!cpu) - continue; - - cpu->enabled = enable_node; - cpu->path.apic.node_id = i; - cpu->path.apic.core_id = j; - printk(BIOS_DEBUG, "CPU: %s %s\n", - dev_path(cpu), cpu->enabled?"enabled":"disabled"); + i, j, apic_id); + + device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + if (cpu) + amd_cpu_topology(cpu, i, j); } //j } return max; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 6fc9434937..063afa9895 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -1060,11 +1060,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; u32 modules = TopologyConfiguration.PlatformNumberOfModules; u32 lapicid_start = 0; - struct device_path cpu_path; - device_t cpu; - /* Build the cpu device path */ - cpu_path.type = DEVICE_PATH_APIC; /* * APIC ID calucation is tightly coupled with AGESA v5 code. * This calculation MUST match the assignment calculation done @@ -1086,23 +1082,13 @@ static u32 cpu_bus_scan(device_t dev, u32 max) lapicid_start = (lapicid_start + 1) * core_max; printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); } - cpu_path.apic.apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); + u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", - i, j, cpu_path.apic.apic_id); - - /* Update CPU in devicetree. */ - if (enable_node) - cpu = alloc_find_dev(cpu_bus, &cpu_path); - else - cpu = find_dev_path(cpu_bus, &cpu_path); - if (!cpu) - continue; - - cpu->enabled = enable_node; - cpu->path.apic.node_id = i; - cpu->path.apic.core_id = j; - printk(BIOS_DEBUG, "CPU: %s %s\n", - dev_path(cpu), cpu->enabled?"enabled":"disabled"); + i, j, apic_id); + + device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + if (cpu) + amd_cpu_topology(cpu, i, j); } //j } return max; diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 34f58ecf3f..c73b38c8a4 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1344,6 +1344,10 @@ static u32 cpu_bus_scan(device_t dev, u32 max) #endif /* Find which cpus are present */ cpu_bus = dev->link_list; + + /* Always use the devicetree node with lapic_id 0 for BSP. */ + remap_bsp_lapic(cpu_bus); + for(i = 0; i < nodes; i++) { device_t cdb_dev; unsigned busn, devn; @@ -1406,34 +1410,18 @@ static u32 cpu_bus_scan(device_t dev, u32 max) } for (j = 0; j <=jj; j++ ) { - struct device_path cpu_path; - device_t cpu; - - /* Build the cpu device path */ - cpu_path.type = DEVICE_PATH_APIC; - cpu_path.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:64); // ? - - /* Update CPU in devicetree. */ - if (enable_node) - cpu = alloc_find_dev(cpu_bus, &cpu_path); - else - cpu = find_dev_path(cpu_bus, &cpu_path); - if (!cpu) - continue; + u32 apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:64); // ? #if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET>0) if(sysconf.enabled_apic_ext_id) { - if (cpu->path.apic.apic_id != 0 || sysconf.lift_bsp_apicid) { - cpu->path.apic.apic_id += sysconf.apicid_offset; + if (apic_id != 0 || sysconf.lift_bsp_apicid) { + apic_id += sysconf.apicid_offset; } } #endif - cpu->enabled = enable_node; - cpu->path.apic.node_id = i; - cpu->path.apic.core_id = j; - printk(BIOS_DEBUG, "CPU: %s %s\n", - dev_path(cpu), cpu->enabled?"enabled":"disabled"); - + device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + if (cpu) + amd_cpu_topology(cpu, i, j); } //j } return max; diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 65e66ab759..9f2fe66c29 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -1238,6 +1238,10 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; + + /* Always use the devicetree node with lapic_id 0 for BSP. */ + remap_bsp_lapic(cpu_bus); + for(i = 0; i < sysconf.nodes; i++) { device_t cpu_dev; @@ -1306,38 +1310,18 @@ static u32 cpu_bus_scan(device_t dev, u32 max) { jj = siblings; } -#if 0 - jj = 0; // if create cpu core1 path in amd_siblings by core0 -#endif for (j = 0; j <=jj; j++ ) { - struct device_path cpu_path; - device_t cpu; - - /* Build the cpu device path */ - cpu_path.type = DEVICE_PATH_APIC; - cpu_path.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8); - - /* Update CPU in devicetree. */ - if (enable_node) - cpu = alloc_find_dev(cpu_bus, &cpu_path); - else - cpu = find_dev_path(cpu_bus, &cpu_path); - if (!cpu) - continue; - + u32 apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8); if(sysconf.enabled_apic_ext_id) { - if (cpu->path.apic.apic_id != 0 || sysconf.lift_bsp_apicid) { - cpu->path.apic.apic_id += sysconf.apicid_offset; + if (apic_id != 0 || sysconf.lift_bsp_apicid) { + apic_id += sysconf.apicid_offset; } } - cpu->enabled = enable_node; - cpu->path.apic.node_id = i; - cpu->path.apic.core_id = j; - printk(BIOS_DEBUG, "CPU: %s %s\n", - dev_path(cpu), cpu->enabled?"enabled":"disabled"); - + device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + if (cpu) + amd_cpu_topology(cpu, i, j); } //j } return max; |