diff options
| -rw-r--r-- | src/soc/intel/skylake/finalize.c | 7 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/pmc.h | 3 |
2 files changed, 9 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index f489e4b89b..9cb246ca40 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -143,6 +143,13 @@ static void pch_finalize_script(void) write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); } + /* Disable XTAL shutdown qualification for low power idle. */ + if (config->s0ix_enable) { + reg32 = read32(pmcbase + CIR31C); + reg32 |= XTALSDQDIS; + write32(pmcbase + CIR31C, reg32); + } + /* we should disable Heci1 based on the devicetree policy */ if (config->HeciEnabled == 0) pch_disable_heci(); diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h index 10ea6ae894..4a80917fe4 100644 --- a/src/soc/intel/skylake/include/soc/pmc.h +++ b/src/soc/intel/skylake/include/soc/pmc.h @@ -98,5 +98,6 @@ #define GPE0_DW2_SHIFT 8 #define GBLRST_CAUSE0 0x124 #define GBLRST_CAUSE1 0x128 - +#define CIR31C 0x31c +#define XTALSDQDIS (1 << 22) #endif |