diff options
| -rw-r--r-- | src/arch/riscv/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/arch/riscv/romstage.c (renamed from src/arch/riscv/stages.c) | 9 |
2 files changed, 1 insertions, 10 deletions
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 16f160e8db..003852324b 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -98,7 +98,7 @@ endif #CONFIG_ARCH_BOOTBLOCK_RISCV ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y) romstage-y += boot.c -romstage-y += stages.c +romstage-y += romstage.c romstage-y += misc.c romstage-$(ARCH_RISCV_PMP) += pmp.c romstage-y += smp.c diff --git a/src/arch/riscv/stages.c b/src/arch/riscv/romstage.c index 5b27508c47..d5f5a43ce1 100644 --- a/src/arch/riscv/stages.c +++ b/src/arch/riscv/romstage.c @@ -14,10 +14,6 @@ */ /* - * This file contains entry/exit functions for each stage during coreboot - * execution (bootblock entry and ramstage exit will depend on external - * loading). - * * Entry points must be placed at the location the previous stage jumps * to (the lowest address in the stage image). This is done by giving * stage_entry() its own section in .text and placing it first in the @@ -31,11 +27,6 @@ void stage_entry(int hart_id, void *fdt) { - /* - * Save the FDT pointer before entering ramstage, because mscratch - * might be overwritten in the trap handler, and there is code in - * ramstage that generates misaligned access faults. - */ HLS()->hart_id = hart_id; HLS()->fdt = fdt; smp_pause(CONFIG_RISCV_WORKING_HARTID); |