diff options
| -rw-r--r-- | src/northbridge/intel/haswell/bootblock.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c index 64e2258c46..0bb8ae2aad 100644 --- a/src/northbridge/intel/haswell/bootblock.c +++ b/src/northbridge/intel/haswell/bootblock.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/bootblock.h> +#include <arch/pci_io_cfg.h> #include <assert.h> -#include <device/pci_ops.h> #include <types.h> + #include "haswell.h" static uint32_t encode_pciexbar_length(void) @@ -28,7 +29,7 @@ void bootblock_early_northbridge_init(void) * * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ - const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0); - pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg); + pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32); } |