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-rw-r--r--src/soc/intel/cannonlake/bootblock/pch.c11
-rw-r--r--src/soc/intel/cannonlake/graphics.c5
2 files changed, 7 insertions, 9 deletions
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index d67edea21c..516359daec 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -61,22 +61,21 @@ static uint32_t get_pmc_reg_base(void)
static void soc_config_pwrmbase(void)
{
uint32_t reg32;
+ uint16_t reg16;
/*
* Assign Resources to PWRMBASE
* Clear BIT 1-2 Command Register
*/
- reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);
- reg32 &= ~(PCI_COMMAND_MEMORY);
- pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
+ reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND);
+ reg16 &= ~(PCI_COMMAND_MEMORY);
+ pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16);
/* Program PWRM Base */
pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
/* Enable Bus Master and MMIO Space */
- reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);
- reg32 |= PCI_COMMAND_MEMORY;
- pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
+ pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY);
/* Enable PWRM in PMC */
reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL));
diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c
index c2f99570b7..1ecbb67098 100644
--- a/src/soc/intel/cannonlake/graphics.c
+++ b/src/soc/intel/cannonlake/graphics.c
@@ -48,9 +48,8 @@ void graphics_soc_init(struct device *dev)
}
/* IGD needs to Bus Master */
- uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
- pci_write_config32(dev, PCI_COMMAND, reg32);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY |
+ PCI_COMMAND_IO);
/*
* GFX PEIM module inside FSP binary is taking care of graphics