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-rw-r--r--src/mainboard/51nb/x210/devicetree.cb2
-rw-r--r--src/mainboard/kontron/bsl6/devicetree.cb1
-rw-r--r--src/soc/intel/skylake/chip.c1
-rw-r--r--src/soc/intel/skylake/chip.h5
4 files changed, 0 insertions, 9 deletions
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb
index 43f272e5a8..b51c73c486 100644
--- a/src/mainboard/51nb/x210/devicetree.cb
+++ b/src/mainboard/51nb/x210/devicetree.cb
@@ -56,8 +56,6 @@ chip soc/intel/skylake
register "serirq_mode" = "SERIRQ_CONTINUOUS"
- register "PmConfigPciClockRun" = "1"
-
# Enable Root Ports 3, 4 and 9
register "PcieRpEnable[2]" = "1" # Ethernet controller
register "PcieRpClkReqSupport[2]" = "1"
diff --git a/src/mainboard/kontron/bsl6/devicetree.cb b/src/mainboard/kontron/bsl6/devicetree.cb
index 6bdfcaf501..8ad785251d 100644
--- a/src/mainboard/kontron/bsl6/devicetree.cb
+++ b/src/mainboard/kontron/bsl6/devicetree.cb
@@ -10,7 +10,6 @@ chip soc/intel/skylake
register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S"
register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S"
register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S"
- register "PmConfigPciClockRun" = "1"
register "PmConfigPwrCycDur" = "RESET_POWER_CYCLE_4S"
# VR Settings Configuration for 2 Domains
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index c9519cdc29..ef16f388d7 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -338,7 +338,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchPmSlpS4MinAssert = config->PmConfigSlpS4MinAssert;
params->PchPmSlpSusMinAssert = config->PmConfigSlpSusMinAssert;
params->PchPmSlpAMinAssert = config->PmConfigSlpAMinAssert;
- params->PchPmLpcClockRun = config->PmConfigPciClockRun;
params->PchPmSlpStrchSusUp = config->PmConfigSlpStrchSusUp;
params->PchPmPwrBtnOverridePeriod =
config->PmConfigPwrBtnOverridePeriod;
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index f4744c9631..7d9d93460c 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -377,11 +377,6 @@ struct soc_intel_skylake_config {
} PmConfigSlpAMinAssert;
/*
- * This member describes whether or not the PCI ClockRun feature of PCH
- * should be enabled. Values 0: Disabled, 1: Enabled
- */
- u8 PmConfigPciClockRun;
- /*
* SLP_X Stretching After SUS Well Power Up. Values 0: Disabled,
* 1: Enabled
*/