diff options
| -rw-r--r-- | src/soc/intel/apollolake/acpi.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/nhlt.c | 22 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/romstage.c | 59 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/tsc_freq.c | 3 |
4 files changed, 43 insertions, 43 deletions
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 56d77323d9..8f9247579f 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -58,7 +58,7 @@ static int acpi_sci_irq(void) static unsigned long acpi_madt_irq_overrides(unsigned long current) { int sci = acpi_sci_irq(); - uint16_t flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW;; + uint16_t flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW; /* INT_SRC_OVR */ current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0); diff --git a/src/soc/intel/apollolake/nhlt.c b/src/soc/intel/apollolake/nhlt.c index b43a34ea31..a86da88fa2 100644 --- a/src/soc/intel/apollolake/nhlt.c +++ b/src/soc/intel/apollolake/nhlt.c @@ -183,17 +183,17 @@ static const struct nhlt_endp_descriptor max98357_descriptors[] = { int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels) { switch (num_channels) { - case 1: - return nhlt_add_endpoints(nhlt, dmic_1ch_descriptors, - ARRAY_SIZE(dmic_1ch_descriptors)); - case 2: - return nhlt_add_endpoints(nhlt, dmic_2ch_descriptors, - ARRAY_SIZE(dmic_2ch_descriptors)); - case 4: - return nhlt_add_endpoints(nhlt, dmic_4ch_descriptors, - ARRAY_SIZE(dmic_4ch_descriptors)); - default: - return -1; + case 1: + return nhlt_add_endpoints(nhlt, dmic_1ch_descriptors, + ARRAY_SIZE(dmic_1ch_descriptors)); + case 2: + return nhlt_add_endpoints(nhlt, dmic_2ch_descriptors, + ARRAY_SIZE(dmic_2ch_descriptors)); + case 4: + return nhlt_add_endpoints(nhlt, dmic_4ch_descriptors, + ARRAY_SIZE(dmic_4ch_descriptors)); + default: + return -1; } } diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 97be0f6213..9a153b34f4 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -136,38 +136,37 @@ static bool punit_init(void) reg = read32(bios_rest_cpl); if (reg == 0xffffffff) { /* P-unit not found */ - printk(BIOS_DEBUG, "Punit MMIO not available \n"); + printk(BIOS_DEBUG, "Punit MMIO not available\n"); return false; - } else { - /* Set Punit interrupt pin IPIN offset 3D */ - pci_write_config8(PUNIT_DEVFN, PCI_INTERRUPT_PIN, 0x2); - - /* Set PUINT IRQ to 24 and INTPIN LOCK */ - write32((void *)(MCH_BASE_ADDR + PUNIT_THERMAL_DEVICE_IRQ), - PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER | - PUINT_THERMAL_DEVICE_IRQ_LOCK); - - data = read32((void *)(MCH_BASE_ADDR + 0x7818)); - data &= 0xFFFFE01F; - data |= 0x20 | 0x200; - write32((void *)(MCH_BASE_ADDR + 0x7818), data); - - /* Stage0 BIOS Reset Complete (RST_CPL) */ - write32(bios_rest_cpl, 0x1); - - /* - * Poll for bit 8 in same reg (RST_CPL). - * We wait here till 1 ms for the bit to get set. - */ - stopwatch_init_msecs_expire(&sw, 1); - while (!(read32(bios_rest_cpl) & 0x100)) { - if (stopwatch_expired(&sw)) { - printk(BIOS_DEBUG, - "Failed to set RST_CPL bit\n"); - return false; - } - udelay(100); + } + /* Set Punit interrupt pin IPIN offset 3D */ + pci_write_config8(PUNIT_DEVFN, PCI_INTERRUPT_PIN, 0x2); + + /* Set PUINT IRQ to 24 and INTPIN LOCK */ + write32((void *)(MCH_BASE_ADDR + PUNIT_THERMAL_DEVICE_IRQ), + PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER | + PUINT_THERMAL_DEVICE_IRQ_LOCK); + + data = read32((void *)(MCH_BASE_ADDR + 0x7818)); + data &= 0xFFFFE01F; + data |= 0x20 | 0x200; + write32((void *)(MCH_BASE_ADDR + 0x7818), data); + + /* Stage0 BIOS Reset Complete (RST_CPL) */ + write32(bios_rest_cpl, 0x1); + + /* + * Poll for bit 8 in same reg (RST_CPL). + * We wait here till 1 ms for the bit to get set. + */ + stopwatch_init_msecs_expire(&sw, 1); + while (!(read32(bios_rest_cpl) & 0x100)) { + if (stopwatch_expired(&sw)) { + printk(BIOS_DEBUG, + "Failed to set RST_CPL bit\n"); + return false; } + udelay(100); } return true; } diff --git a/src/soc/intel/apollolake/tsc_freq.c b/src/soc/intel/apollolake/tsc_freq.c index 3bd709c03d..f91a047d08 100644 --- a/src/soc/intel/apollolake/tsc_freq.c +++ b/src/soc/intel/apollolake/tsc_freq.c @@ -37,7 +37,8 @@ void set_max_freq(void) eax = cpuid_eax(CPUID_LEAF_PM); msr = rdmsr(MSR_IA32_MISC_ENABLES); - if (!(eax &= 0x2) && ((msr.hi & APL_BURST_MODE_DISABLE) == 0)) { + eax &= 0x2; + if ((!eax) && ((msr.hi & APL_BURST_MODE_DISABLE) == 0)) { /* Burst Mode has been factory configured as disabled * and is not available in this physical processor * package. |