diff options
| -rw-r--r-- | src/mainboard/google/nyan/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/google/nyan_big/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/google/nyan_blaze/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra124/chip.h | 1 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra124/display.c | 2 |
5 files changed, 1 insertions, 8 deletions
diff --git a/src/mainboard/google/nyan/devicetree.cb b/src/mainboard/google/nyan/devicetree.cb index 1031b029fe..5db8192ac9 100644 --- a/src/mainboard/google/nyan/devicetree.cb +++ b/src/mainboard/google/nyan/devicetree.cb @@ -32,8 +32,6 @@ chip soc/nvidia/tegra124 register "panel_bits_per_pixel" = "18" - register "cache_policy" = "DCACHE_WRITETHROUGH" - # With some help from the mainbaord designer register "backlight_en_gpio" = "GPIO(H2)" register "lvds_shutdown_gpio" = "0" diff --git a/src/mainboard/google/nyan_big/devicetree.cb b/src/mainboard/google/nyan_big/devicetree.cb index 1031b029fe..5db8192ac9 100644 --- a/src/mainboard/google/nyan_big/devicetree.cb +++ b/src/mainboard/google/nyan_big/devicetree.cb @@ -32,8 +32,6 @@ chip soc/nvidia/tegra124 register "panel_bits_per_pixel" = "18" - register "cache_policy" = "DCACHE_WRITETHROUGH" - # With some help from the mainbaord designer register "backlight_en_gpio" = "GPIO(H2)" register "lvds_shutdown_gpio" = "0" diff --git a/src/mainboard/google/nyan_blaze/devicetree.cb b/src/mainboard/google/nyan_blaze/devicetree.cb index 1031b029fe..5db8192ac9 100644 --- a/src/mainboard/google/nyan_blaze/devicetree.cb +++ b/src/mainboard/google/nyan_blaze/devicetree.cb @@ -32,8 +32,6 @@ chip soc/nvidia/tegra124 register "panel_bits_per_pixel" = "18" - register "cache_policy" = "DCACHE_WRITETHROUGH" - # With some help from the mainbaord designer register "backlight_en_gpio" = "GPIO(H2)" register "lvds_shutdown_gpio" = "0" diff --git a/src/soc/nvidia/tegra124/chip.h b/src/soc/nvidia/tegra124/chip.h index 186657f02f..6994ca2210 100644 --- a/src/soc/nvidia/tegra124/chip.h +++ b/src/soc/nvidia/tegra124/chip.h @@ -32,7 +32,6 @@ struct soc_nvidia_tegra124_config { u32 framebuffer_bits_per_pixel; u32 color_depth; u32 panel_bits_per_pixel; - int cache_policy; /* there are two. It's not unimaginable that we might someday * have two of these structs in a single mainboard. */ diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 9ec34d481f..dce6ad257a 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -263,7 +263,7 @@ void display_startup(device_t dev) config->framebuffer_base = framebuffer_base_mb * MiB; mmu_config_range(framebuffer_base_mb, framebuffer_size_mb, - config->cache_policy); + DCACHE_WRITETHROUGH); printk(BIOS_SPEW, "LCD frame buffer at %dMiB to %dMiB\n", framebuffer_base_mb, framebuffer_base_mb + framebuffer_size_mb); |