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-rw-r--r--src/include/cpu/amd/amdfam12.h1
-rw-r--r--src/northbridge/amd/agesa/family12/northbridge.c19
-rw-r--r--src/northbridge/amd/agesa/family12/northbridge.h2
-rw-r--r--src/vendorcode/amd/agesa/f12/AGESA.h4
-rw-r--r--src/vendorcode/amd/agesa/f12/Legacy/Proc/Dispatcher.c6
-rw-r--r--src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c8
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/CPU/S3.c4
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/CPU/cpuApicUtilities.c4
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/CPU/cpuMicrocodePatch.c2
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPostInit.c2
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c40
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Common/AmdS3LateRestore.c2
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Common/AmdS3Save.c6
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/GNB/Common/Gnb.h2
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c4
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h4
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoComplexData.h2
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/PcieFamilyServices.h7
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/S3/mfs3.c10
19 files changed, 70 insertions, 59 deletions
diff --git a/src/include/cpu/amd/amdfam12.h b/src/include/cpu/amd/amdfam12.h
index cabd532f2e..905fead98c 100644
--- a/src/include/cpu/amd/amdfam12.h
+++ b/src/include/cpu/amd/amdfam12.h
@@ -49,6 +49,5 @@ void wait_all_aps_started(u32 bsp_apicid);
void allow_all_aps_stop(u32 bsp_apicid);
#endif
void get_bus_conf(void);
-u32 get_initial_apicid(void);
#endif /* CPU_AMD_FAM12_H */
diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c
index a4ed87f891..1467fdcfd2 100644
--- a/src/northbridge/amd/agesa/family12/northbridge.c
+++ b/src/northbridge/amd/agesa/family12/northbridge.c
@@ -299,7 +299,6 @@ struct hw_mem_hole_info {
static struct hw_mem_hole_info get_hw_mem_hole_info(void)
{
struct hw_mem_hole_info mem_hole;
- int i;
mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
mem_hole.node_id = -1;
@@ -582,10 +581,8 @@ static void domain_read_resources(device_t dev)
static void domain_set_resources(device_t dev)
{
- u32 val;
printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
- printk(BIOS_DEBUG, " amsr - incoming dev = %08lx\n",dev);
-
+ printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev);
#if CONFIG_PCI_64BIT_PREF_MEM
struct resource *io, *mem1, *mem2;
@@ -593,7 +590,7 @@ static void domain_set_resources(device_t dev)
#endif
unsigned long mmio_basek;
u32 pci_tolm;
- int i, idx;
+ int idx;
struct bus *link;
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
struct hw_mem_hole_info mem_hole;
@@ -712,8 +709,9 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n");
sizek = limitk - 768;
}
-
-printk(BIOS_DEBUG, "adsr: mmio_basek=%08x, basek=%08x, limitk=%08x\n", mmio_basek, basek, limitk);
+ printk(BIOS_DEBUG,
+ "adsr: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
+ mmio_basek, basek, limitk);
/* split the region to accomodate pci memory space */
if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
@@ -760,7 +758,7 @@ printk(BIOS_DEBUG, "adsr: mmio_basek=%08x, basek=%08x, limitk=%08x\n", mmio_bas
/* Leave some space for ACPI, PIRQ and MP tables */
#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
- printk(BIOS_DEBUG, " adsr - uma_memory_base = %x.\n",uma_memory_base);
+ printk(BIOS_DEBUG, " adsr - uma_memory_base = %llx.\n", uma_memory_base);
#else
high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE;
#endif
@@ -768,8 +766,9 @@ printk(BIOS_DEBUG, "adsr: mmio_basek=%08x, basek=%08x, limitk=%08x\n", mmio_bas
}
#endif
}
-printk(BIOS_DEBUG, " adsr - mmio_basek = %x.\n",mmio_basek);
-printk(BIOS_DEBUG, " adsr - high_tables_size = %x.\n",high_tables_size);
+ printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek);
+ printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n",
+ high_tables_size);
#if CONFIG_GFXUMA
uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10);
diff --git a/src/northbridge/amd/agesa/family12/northbridge.h b/src/northbridge/amd/agesa/family12/northbridge.h
index 8de80ff501..d5c12f25e1 100644
--- a/src/northbridge/amd/agesa/family12/northbridge.h
+++ b/src/northbridge/amd/agesa/family12/northbridge.h
@@ -23,4 +23,6 @@
static struct device_operations pci_domain_ops;
static struct device_operations cpu_bus_ops;
+device_t get_node_pci(u32 nodeid, u32 fn);
+
#endif /* NORTHBRIDGE_AMD_AGESA_FAM12H_H */
diff --git a/src/vendorcode/amd/agesa/f12/AGESA.h b/src/vendorcode/amd/agesa/f12/AGESA.h
index b939eb4429..9f618079f3 100644
--- a/src/vendorcode/amd/agesa/f12/AGESA.h
+++ b/src/vendorcode/amd/agesa/f12/AGESA.h
@@ -1279,8 +1279,12 @@ typedef enum {
///< CPU MSR Register definitions ------------------------------------------
#define SYS_CFG 0xC0010010
+#ifndef TOP_MEM
#define TOP_MEM 0xC001001A
+#endif
+#ifndef TOP_MEM2
#define TOP_MEM2 0xC001001D
+#endif
#define HWCR 0xC0010015
#define NB_CFG 0xC001001F
diff --git a/src/vendorcode/amd/agesa/f12/Legacy/Proc/Dispatcher.c b/src/vendorcode/amd/agesa/f12/Legacy/Proc/Dispatcher.c
index 1c2a8c23c7..865c84fab4 100644
--- a/src/vendorcode/amd/agesa/f12/Legacy/Proc/Dispatcher.c
+++ b/src/vendorcode/amd/agesa/f12/Legacy/Proc/Dispatcher.c
@@ -104,7 +104,7 @@ AmdAgesaDispatcher (
// 2. Try next dispatcher if possible, and we have not already got status back
if ((mCpuModuleID.NextBlock != NULL) && (Status == AGESA_UNSUPPORTED)) {
- ModuleEntry = (MODULE_ENTRY) (UINT64) mCpuModuleID.NextBlock->ModuleDispatcher;
+ ModuleEntry = (MODULE_ENTRY) (intptr_t) mCpuModuleID.NextBlock->ModuleDispatcher;
if (ModuleEntry != NULL) {
Status = (*ModuleEntry) (ConfigPtr);
}
@@ -116,10 +116,10 @@ AmdAgesaDispatcher (
ImageStart = ((AMD_CONFIG_PARAMS *)ConfigPtr)->AltImageBasePtr;
ImageEnd = ImageStart + 4;
// Locate/test image base that matches this component
- AltImagePtr = LibAmdLocateImage ((VOID *) (UINT64)ImageStart, (VOID *) (UINT64)ImageEnd, 4096, (CHAR8 *)AGESA_ID);
+ AltImagePtr = LibAmdLocateImage ((VOID *) (intptr_t) ImageStart, (VOID *) (intptr_t) ImageEnd, 4096, (CHAR8 *)AGESA_ID);
if (AltImagePtr != NULL) {
//Invoke alternative Image
- ImageEntry = (IMAGE_ENTRY) ((UINT64) AltImagePtr + AltImagePtr->EntryPointAddress);
+ ImageEntry = (IMAGE_ENTRY) ((intptr_t) AltImagePtr + AltImagePtr->EntryPointAddress);
Status = (*ImageEntry) (ConfigPtr);
}
}
diff --git a/src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c
index c4a790a4cb..bf8e6d206d 100644
--- a/src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c
+++ b/src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c
@@ -208,12 +208,12 @@ CopyHeapToTempRamAtPost (
TotalSize = sizeof (HEAP_MANAGER);
SizeOfNodeData = 0;
AlignTo16ByteInTempMem = 0;
- BaseAddressInCache = (UINT8 *) StdHeader->HeapBasePtr;
+ BaseAddressInCache = (UINT8 *) (intptr_t) StdHeader->HeapBasePtr;
HeapManagerInCache = (HEAP_MANAGER *) BaseAddressInCache;
HeapInCacheOffset = HeapManagerInCache->FirstActiveBufferOffset;
HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset);
- BaseAddressInTempMem = (UINT8 *) UserOptions.CfgHeapDramAddress;
+ BaseAddressInTempMem = (UINT8 *) (intptr_t) UserOptions.CfgHeapDramAddress;
HeapManagerInTempMem = (HEAP_MANAGER *) BaseAddressInTempMem;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize);
@@ -307,8 +307,8 @@ CopyHeapToMainRamAtPost (
TotalSize = sizeof (HEAP_MANAGER);
SizeOfNodeData = 0;
AlignTo16ByteInMainMem = 0;
- BaseAddressInTempMem = (UINT8 *) StdHeader->HeapBasePtr;
- HeapManagerInTempMem = (HEAP_MANAGER *) StdHeader->HeapBasePtr;
+ BaseAddressInTempMem = (UINT8 *) (intptr_t) StdHeader->HeapBasePtr;
+ HeapManagerInTempMem = (HEAP_MANAGER *) (intptr_t) StdHeader->HeapBasePtr;
HeapInTempMemOffset = HeapManagerInTempMem->FirstActiveBufferOffset;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset);
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/S3.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/S3.c
index 4a5fb91f14..6174e07382 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/S3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/S3.c
@@ -216,7 +216,7 @@ SaveDeviceContext (
UINT64 EndAddress;
VOID *OrMask;
- StartAddress = (UINT64) DeviceList;
+ StartAddress = (UINT64) (intptr_t) DeviceList;
Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1];
OrMask = (UINT8 *) DeviceList + DeviceList->RelativeOrMaskOffset;
@@ -280,7 +280,7 @@ SaveDeviceContext (
break;
}
}
- EndAddress = (UINT64) OrMask;
+ EndAddress = (UINT64) (intptr_t) OrMask;
*ActualBufferSize = (UINT32) (EndAddress - StartAddress);
}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuApicUtilities.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuApicUtilities.c
index 37a84f7fe6..06a1d7b085 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuApicUtilities.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuApicUtilities.c
@@ -807,7 +807,7 @@ ApUtilSetupIdtForHlt (
DescSize = 8;
}
- HandlerOffset = (UINT64) NmiHandler;
+ HandlerOffset = (UINT64) (intptr_t) NmiHandler;
NmiIdtDescPtr->OffsetLo = (UINT16) HandlerOffset & 0xFFFF;
NmiIdtDescPtr->OffsetHi = (UINT16) (HandlerOffset >> 16);
GetCsSelector (&NmiIdtDescPtr->Selector, StdHeader);
@@ -816,7 +816,7 @@ ApUtilSetupIdtForHlt (
NmiIdtDescPtr->Offset64 = (UINT32) (HandlerOffset >> 32);
NmiIdtDescPtr->Rsvd64 = 0;
IdtInfo.Limit = (UINT16) ((DescSize * 3) - 1);
- IdtInfo.Base = (UINT64) NmiIdtDescPtr - (DescSize * 2);
+ IdtInfo.Base = (UINT64) (intptr_t) NmiIdtDescPtr - (DescSize * 2);
// IDS_EXCEPTION_TRAP (IDS_IDT_UPDATE_EXCEPTION_VECTOR_FOR_AP, &IdtInfo, StdHeader);
SetIdtr (&IdtInfo , StdHeader);
}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuMicrocodePatch.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuMicrocodePatch.c
index c4d408aa6e..2d9b2216a2 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuMicrocodePatch.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuMicrocodePatch.c
@@ -205,7 +205,7 @@ LoadMicrocode (
PATCH_LOADER PatchLoaderMsr;
// Load microcode patch into CPU
- PatchLoaderMsr.RawData = (UINT64) MicrocodePatchPtr;
+ PatchLoaderMsr.RawData = (UINT64) (intptr_t) MicrocodePatchPtr;
PatchLoaderMsr.BitFields.SBZ = 0;
LibAmdMsrWrite (MSR_PATCH_LOADER, &PatchLoaderMsr.RawData, StdHeader);
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPostInit.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPostInit.c
index 5b90207089..2c87c2b24c 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPostInit.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPostInit.c
@@ -217,7 +217,7 @@ GetPstateGatherDataAddressAtPost (
AddressValue = P_STATE_DATA_GATHER_TEMP_ADDR;
- *Ptr = (UINT64 *)(AddressValue);
+ *Ptr = (UINT64 *) (intptr_t) (AddressValue);
return AGESA_SUCCESS;
}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c
index e45cb0b010..dacadedc14 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c
@@ -155,13 +155,13 @@ HeapManagerInit (
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &Ignored, StdHeader);
- HeapBufferPtr = (UINT8 *) StdHeader->HeapBasePtr;
+ HeapBufferPtr = (UINT8 *) (intptr_t) StdHeader->HeapBasePtr;
// Check whether the heap manager is already initialized
LibAmdMsrRead (AMD_MTRR_VARIABLE_HEAP_MASK, &MsrData, StdHeader);
if (MsrData == (CacheInfoPtr->VariableMtrrMask & (UINT64) AMD_HEAP_MTRR_MASK)) {
LibAmdMsrRead (AMD_MTRR_VARIABLE_HEAP_BASE, &MsrData, StdHeader);
- if ((MsrData & CacheInfoPtr->HeapBaseMask) == ((UINT64) HeapBufferPtr & CacheInfoPtr->HeapBaseMask)) {
+ if ((MsrData & CacheInfoPtr->HeapBaseMask) == ((UINT64) (intptr_t) HeapBufferPtr & CacheInfoPtr->HeapBaseMask)) {
if (((HEAP_MANAGER *) HeapBufferPtr)->Signature == HEAP_SIGNATURE_VALID) {
// This is not a bug, there are multiple premem basic entry points,
// and each will call heap init to make sure create struct will succeed.
@@ -177,7 +177,7 @@ HeapManagerInit (
}
// Set variable MTRR base and mask
- MsrData = ((UINT64) HeapBufferPtr & CacheInfoPtr->HeapBaseMask);
+ MsrData = ((UINT64) (intptr_t) HeapBufferPtr & CacheInfoPtr->HeapBaseMask);
MsrMask = CacheInfoPtr->VariableMtrrHeapMask & (UINT64) AMD_HEAP_MTRR_MASK;
MsrData |= 0x06;
@@ -306,20 +306,20 @@ HeapAllocateBuffer (
AllocateHeapParams->RequestedBufferSize += NUM_OF_SENTINEL * SIZE_OF_SENTINEL;
// Get base address
- BaseAddress = (UINT8 *) StdHeader->HeapBasePtr;
+ BaseAddress = (UINT8 *) (intptr_t) StdHeader->HeapBasePtr;
HeapManager = (HEAP_MANAGER *) BaseAddress;
// Check Heap database is valid
if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
// The base address in StdHeader is incorrect, get base address by itself
- BaseAddress = (UINT8 *) HeapGetBaseAddress (StdHeader);
+ BaseAddress = (UINT8 *) (intptr_t) HeapGetBaseAddress (StdHeader);
HeapManager = (HEAP_MANAGER *) BaseAddress;
if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
// Heap is not available, ASSERT here
ASSERT (FALSE);
return AGESA_ERROR;
}
- StdHeader->HeapBasePtr = (UINT64) BaseAddress;
+ StdHeader->HeapBasePtr = (UINT64) (intptr_t) BaseAddress;
}
// Allocate
@@ -451,20 +451,20 @@ HeapDeallocateBuffer (
ASSERT (StdHeader != NULL);
HeapLocateFlag = TRUE;
- BaseAddress = (UINT8 *) StdHeader->HeapBasePtr;
+ BaseAddress = (UINT8 *) (intptr_t) StdHeader->HeapBasePtr;
HeapManager = (HEAP_MANAGER *) BaseAddress;
// Check Heap database is valid
if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
// The base address in StdHeader is incorrect, get base address by itself
- BaseAddress = (UINT8 *) HeapGetBaseAddress (StdHeader);
+ BaseAddress = (UINT8 *) (intptr_t) HeapGetBaseAddress (StdHeader);
HeapManager = (HEAP_MANAGER *) BaseAddress;
if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
// Heap is not available, ASSERT here
ASSERT (FALSE);
return AGESA_ERROR;
}
- StdHeader->HeapBasePtr = (UINT64) BaseAddress;
+ StdHeader->HeapBasePtr = (UINT64) (intptr_t) BaseAddress;
}
OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET;
@@ -580,20 +580,20 @@ HeapLocateBuffer (
ASSERT (StdHeader != NULL);
HeapLocateFlag = TRUE;
- BaseAddress = (UINT8 *) StdHeader->HeapBasePtr;
+ BaseAddress = (UINT8 *) (intptr_t) StdHeader->HeapBasePtr;
HeapManager = (HEAP_MANAGER *) BaseAddress;
// Check Heap database is valid
if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
// The base address in StdHeader is incorrect, get base address by itself
- BaseAddress = (UINT8 *) HeapGetBaseAddress (StdHeader);
+ BaseAddress = (UINT8 *) (intptr_t) HeapGetBaseAddress (StdHeader);
HeapManager = (HEAP_MANAGER *) BaseAddress;
if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
// Heap is not available, ASSERT here
ASSERT (FALSE);
return AGESA_ERROR;
}
- StdHeader->HeapBasePtr = (UINT64) BaseAddress;
+ StdHeader->HeapBasePtr = (UINT64) (intptr_t) BaseAddress;
}
OffsetOfCurrentNode = HeapManager->FirstActiveBufferOffset;
CurrentNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode);
@@ -684,29 +684,29 @@ HeapGetBaseAddress (
// Firstly, we try to see if heap is in cache
BaseAddress = HeapGetCurrentBase (StdHeader);
- HeapManager = (HEAP_MANAGER *) BaseAddress;
+ HeapManager = (HEAP_MANAGER *) (intptr_t) BaseAddress;
if ((HeapManager->Signature != HEAP_SIGNATURE_VALID) &&
(StdHeader->HeapStatus != HEAP_DO_NOT_EXIST_YET) &&
(StdHeader->HeapStatus != HEAP_LOCAL_CACHE)) {
// Secondly, we try to see if heap is in temp memory
BaseAddress = UserOptions.CfgHeapDramAddress;
- HeapManager = (HEAP_MANAGER *) BaseAddress;
+ HeapManager = (HEAP_MANAGER *) (intptr_t) BaseAddress;
if (HeapManager->Signature != HEAP_SIGNATURE_VALID) {
// Thirdly, we try to see if heap in main memory
// by locating with external buffer manager (IBV)
AgesaBuffer.StdHeader = *StdHeader;
AgesaBuffer.BufferHandle = AMD_HEAP_IN_MAIN_MEMORY_HANDLE;
if (AgesaLocateBuffer (0, &AgesaBuffer) == AGESA_SUCCESS) {
- BaseAddress = (UINT64) AgesaBuffer.BufferPointer;
- HeapManager = (HEAP_MANAGER *) BaseAddress;
+ BaseAddress = (UINT64) (intptr_t) AgesaBuffer.BufferPointer;
+ HeapManager = (HEAP_MANAGER *) (intptr_t) BaseAddress;
if (HeapManager->Signature != HEAP_SIGNATURE_VALID) {
// No valid heap signature ever found, return a NULL pointer
- BaseAddress = NULL;
+ BaseAddress = (UINT64) (intptr_t) NULL;
}
} else {
// No heap buffer is allocated by external manager (IBV), return a NULL pointer
- BaseAddress = NULL;
+ BaseAddress = (UINT64) (intptr_t) NULL;
}
}
}
@@ -748,7 +748,7 @@ DeleteFreeSpaceNode (
BUFFER_NODE *PreviousFreeSpaceNode;
- BaseAddress = (UINT8 *) StdHeader->HeapBasePtr;
+ BaseAddress = (UINT8 *) (intptr_t) StdHeader->HeapBasePtr;
HeapManager = (HEAP_MANAGER *) BaseAddress;
OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET;
@@ -807,7 +807,7 @@ InsertFreeSpaceNode (
BUFFER_NODE *PreviousFreeSpaceNode;
BUFFER_NODE *LocalInsertFreeSpaceNode;
- BaseAddress = (UINT8 *) StdHeader->HeapBasePtr;
+ BaseAddress = (UINT8 *) (intptr_t) StdHeader->HeapBasePtr;
HeapManager = (HEAP_MANAGER *) BaseAddress;
OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET;
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdS3LateRestore.c b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdS3LateRestore.c
index d2a0bf03dc..01665da5ca 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdS3LateRestore.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdS3LateRestore.c
@@ -119,7 +119,7 @@ AmdS3LateRestore (
ASSERT (S3LateParams != NULL);
BufferPointer = (UINT8 *) S3LateParams->S3DataBlock.VolatileStorage;
- S3LateParams->StdHeader.HeapBasePtr = (UINT64)((UINT8 *)(&BufferPointer[(((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->HeapOffset)]));
+ S3LateParams->StdHeader.HeapBasePtr = (UINT64) (intptr_t) ((UINT8 *)(&BufferPointer[(((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->HeapOffset)]));
ASSERT (S3LateParams->StdHeader.HeapBasePtr != 0);
IDS_HDT_CONSOLE_INIT (&S3LateParams->StdHeader);
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdS3Save.c b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdS3Save.c
index ae07e42406..66a6fa7d15 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Common/AmdS3Save.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Common/AmdS3Save.c
@@ -227,9 +227,9 @@ AmdS3Save (
BufferPointer = AllocParams.BufferPtr;
AmdS3SaveParams->S3DataBlock.VolatileStorage = &(BufferPointer[EarlyBufferSize]);
- ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->HeapOffset = NULL;
+ ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->HeapOffset = (intptr_t) NULL;
((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->HeapSize = HeapSize;
- ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->RegisterDataOffset = NULL;
+ ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->RegisterDataOffset = (intptr_t) NULL;
((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->RegisterDataSize = LateContextSize;
if (HeapSize != 0) {
@@ -246,7 +246,7 @@ AmdS3Save (
HeapStatus = AmdS3SaveParams->StdHeader.HeapStatus;
AmdS3SaveParams->StdHeader.HeapStatus = HEAP_S3_RESUME;
- AmdS3SaveParams->StdHeader.HeapBasePtr = (UINT64) HeapPtr;
+ AmdS3SaveParams->StdHeader.HeapBasePtr = (UINT64) (intptr_t) HeapPtr;
for (i = 0; i < S3LATE_TABLE_SIZE; i++) {
if (HeapPtrs[i] != NULL) {
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/Gnb.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/Gnb.h
index 2842fd7b21..6839ba5f58 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/Gnb.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Common/Gnb.h
@@ -82,7 +82,7 @@
#define PVOID UINT64
-#define GnbLibGetHeader(x) ((AMD_CONFIG_PARAMS*) (x)->StdHeader)
+#define GnbLibGetHeader(x) ((AMD_CONFIG_PARAMS*) (intptr_t) (x)->StdHeader)
#define AGESA_STATUS_UPDATE(Current, Aggregated) \
if (Current > Aggregated) { \
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c
index 6f4f8fb8a3..d69a896645 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c
@@ -195,7 +195,7 @@ PcieConfigBuildData (
return AGESA_FATAL;
}
LibAmdMemFill (Pcie, 0x00, sizeof (PCIe_PLATFORM_CONFIG) + ComplexesDataLength, StdHeader);
- Pcie->StdHeader = (PVOID) StdHeader;
+ Pcie->StdHeader = (PVOID) (intptr_t) StdHeader;
Pcie->Header.Child = offsetof (PCIe_PLATFORM_CONFIG, ComplexList);
PcieConfigSetDescriptorFlags (Pcie, DESCRIPTOR_PLATFORM | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_TOPOLOGY);
Buffer = (UINT8 *) (Pcie) + sizeof (PCIe_PLATFORM_CONFIG);
@@ -422,7 +422,7 @@ PcieLocateConfigurationData (
return AGESA_FATAL;
}
PcieUpdateConfigurationData (*Pcie);
- (*Pcie)->StdHeader = (PVOID) StdHeader;
+ (*Pcie)->StdHeader = (PVOID) (intptr_t) StdHeader;
return AGESA_SUCCESS;
}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h
index e04d4ca0e7..682e336dda 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h
@@ -185,7 +185,7 @@ PcieUserConfigConfigDump (
#define PcieConfigGetChildWrapper(Descriptor) ((PCIe_WRAPPER_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_WRAPPERS, &((Descriptor)->Header)))
#define PcieConfigGetChildEngine(Descriptor) ((PCIe_ENGINE_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_ENGINES, &((Descriptor)->Header)))
#define PcieConfigGetChildSilicon(Descriptor) ((PCIe_SILICON_CONFIG *) PcieConfigGetChild (DESCRIPTOR_SILICON, &((Descriptor)->Header)))
-#define PcieConfigGetNextDescriptor(Descriptor) (Descriptor != NULL ? ((((Descriptor->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : (++Descriptor))) : NULL)
+#define PcieConfigGetNextDescriptor(Descriptor) (Descriptor != NULL ? ((((Descriptor->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : (Descriptor+1))) : NULL)
#define PcieConfigIsPcieEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_ENGINE) != 0) : (1==0))
#define PcieConfigIsDdiEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_DDI_ENGINE) != 0) : (1==0))
#define PcieConfigIsPcieWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_WRAPPER) != 0) : (1==0))
@@ -195,7 +195,7 @@ PcieUserConfigConfigDump (
#define PcieConfigIsVirtualDesciptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_VIRTUAL) != 0) : (1==0))
#define PcieConfigSetDescriptorFlags(Descriptor, SetDescriptorFlags) (Descriptor)->Header.DescriptorFlags |= SetDescriptorFlags
#define PcieConfigResetDescriptorFlags(Descriptor, ResetDescriptorFlags) ((PCIe_DESCRIPTOR_HEADER *) Descriptor)->DescriptorFlags &= (~(ResetDescriptorFlags))
-#define PcieInputParsetGetNextDescriptor(Descriptor) (Descriptor != NULL ? ((((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : (++Descriptor))) : NULL)
+#define PcieInputParsetGetNextDescriptor(Descriptor) (Descriptor != NULL ? ((((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : (Descriptor+1))) : NULL)
#define PcieConfigGetNextTopologyDescriptor(Descriptor, Termination) (((((PCIe_DESCRIPTOR_HEADER *) Descriptor)->DescriptorFlags & Termination) != 0) ? NULL : ((UINT8 *) Descriptor + ((PCIe_DESCRIPTOR_HEADER *) Descriptor)->Peer))
#endif
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoComplexData.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoComplexData.h
index 5fa4f64054..f15374e748 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoComplexData.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoComplexData.h
@@ -117,7 +117,7 @@ F12_COMPLEX_CONFIG ComplexData = {
DDI_NUMBER_OF_PIFs,
DDI_START_PHY_LANE,
DDI_END_PHY_LANE,
- (UINT8)0xff,
+ 0x0f,
0x0,
8,
{
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/PcieFamilyServices.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/PcieFamilyServices.h
index a9a38630c5..bc250c276e 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/PcieFamilyServices.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/PcieFamilyServices.h
@@ -48,6 +48,13 @@
#define _PCIECOMPLEXCONFIG_H_
+AGESA_STATUS
+PcieFmForceDccRecalibrationCallback (
+ IN PCIe_WRAPPER_CONFIG *Wrapper,
+ IN OUT VOID *Buffer,
+ IN PCIe_PLATFORM_CONFIG *Pcie
+ );
+
VOID
PcieFmPhyApplyGanging (
IN PCIe_WRAPPER_CONFIG *Wrapper,
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/S3/mfs3.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/S3/mfs3.c
index fdf0d6bd8a..728bd01d25 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/S3/mfs3.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/S3/mfs3.c
@@ -261,30 +261,30 @@ MemFS3GetDeviceList (
(*DeviceBlockHdrPtr)->RelativeOrMaskOffset = (UINT16) AllocHeapParams.RequestedBufferSize;
// Copy device list on the stack to the heap.
- BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) AllocHeapParams.BufferPtr;
+ BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) (intptr_t) AllocHeapParams.BufferPtr;
for (Die = 0; Die < DieCount; Die ++) {
for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
// Copy PCI device descriptor to the heap if it exists.
if (DeviceDescript[Die].PCIDevice[i].RegisterListID != 0xFFFFFFFF) {
- LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader);
+ LibAmdMemCopy ((VOID *) (intptr_t) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader);
(*DeviceBlockHdrPtr)->NumDevices ++;
BufferOffset += sizeof (PCI_DEVICE_DESCRIPTOR);
}
// Copy conditional PCI device descriptor to the heap if it exists.
if (DeviceDescript[Die].CPCIDevice[i].RegisterListID != 0xFFFFFFFF) {
- LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader);
+ LibAmdMemCopy ((VOID *) (intptr_t) BufferOffset, &(DeviceDescript[Die].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader);
(*DeviceBlockHdrPtr)->NumDevices ++;
BufferOffset += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
}
// Copy MSR device descriptor to the heap if it exists.
if (DeviceDescript[Die].MSRDevice[i].RegisterListID != 0xFFFFFFFF) {
- LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader);
+ LibAmdMemCopy ((VOID *) (intptr_t) BufferOffset, &(DeviceDescript[Die].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader);
(*DeviceBlockHdrPtr)->NumDevices ++;
BufferOffset += sizeof (MSR_DEVICE_DESCRIPTOR);
}
// Copy conditional MSR device descriptor to the heap if it exists.
if (DeviceDescript[Die].CMSRDevice[i].RegisterListID != 0xFFFFFFFF) {
- LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader);
+ LibAmdMemCopy ((VOID *) (intptr_t) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader);
(*DeviceBlockHdrPtr)->NumDevices ++;
BufferOffset += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
}