diff options
| -rw-r--r-- | src/arch/mips/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/arch/mips/bootblock.S | 10 | ||||
| -rw-r--r-- | src/arch/mips/cache.c | 112 | ||||
| -rw-r--r-- | src/arch/mips/include/arch/cache.h | 29 | ||||
| -rw-r--r-- | src/arch/mips/stages.c | 3 |
5 files changed, 144 insertions, 13 deletions
diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc index 1929140867..0539c4fafb 100644 --- a/src/arch/mips/Makefile.inc +++ b/src/arch/mips/Makefile.inc @@ -37,6 +37,7 @@ ifeq ($(CONFIG_ARCH_BOOTBLOCK_MIPS),y) bootblock-y += boot.c bootblock-y += bootblock.S bootblock-y += bootblock_simple.c +bootblock-y += cache.c bootblock-y += stages.c bootblock-y += ../../lib/memcpy.c bootblock-y += ../../lib/memmove.c @@ -62,6 +63,7 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_MIPS),y) romstage-y += boot.c romstage-$(CONFIG_EARLY_CONSOLE) += early_console.c +romstage-y += cache.c romstage-y += stages.c romstage-y += ../../lib/memcpy.c romstage-y += ../../lib/memmove.c @@ -81,6 +83,7 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_MIPS),y) ramstage-y += ashldi3.c ramstage-y += boot.c +ramstage-y += cache.c ramstage-y += stages.c ramstage-y += tables.c ramstage-y += ../../lib/memcpy.c diff --git a/src/arch/mips/bootblock.S b/src/arch/mips/bootblock.S index ed31b24cfa..8899fe0a97 100644 --- a/src/arch/mips/bootblock.S +++ b/src/arch/mips/bootblock.S @@ -36,16 +36,6 @@ _start: bne $t0, $t1, 1b addi $t0, $t0, 4 - /* - * Disable caches for now, proper cache management is coming soon. - * http://crosbug.com/p/34127 - */ - mfc0 $t0, $16 - li $t1, -8 - and $t0, $t0, $t1 - ori $t0, $t0, 2 - mtc0 $t0, $16 - /* Run main */ b main diff --git a/src/arch/mips/cache.c b/src/arch/mips/cache.c new file mode 100644 index 0000000000..209349539d --- /dev/null +++ b/src/arch/mips/cache.c @@ -0,0 +1,112 @@ + +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Imagination Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/cache.h> +#include <symbols.h> + +/* Cache operations */ + +/* + * __get_line_size: + * Read config register + * Isolate instruction cache line size + * Interpret value as per MIPS manual: 2 << value + * Return cache line size + */ +#define __get_line_size(cfg_no, cfg_sel, lshift, nobits) \ +({ int __res; \ + __asm__ __volatile__( \ + ".set push\n\t" \ + ".set noreorder\n\t" \ + ".set mips32\n\t" \ + "mfc0 $t5, "#cfg_no"," #cfg_sel"\n\t" \ + ".set mips0\n\t" \ + "ext $t6, $t5," #lshift"," #nobits"\n\t" \ + "li $t7, 2\n\t" \ + "sllv %0, $t7, $t6\n\t" \ + ".set pop\n\t" \ + : "=r" (__res)); \ + __res; \ +}) + +/* clear_L2tag: clear L23Tag register */ +#define clear_L2tag() \ +({ \ + __asm__ __volatile__( \ + ".set push\n\t" \ + ".set noreorder\n\t" \ + ".set mips32\n\t" \ + "mtc0 $zero, $28, 4\n\t" \ + ".set mips0\n\t" \ + ".set pop\n\t" \ + ); \ +}) + +/* cache_op: issues cache operation for specified address */ +#define cache_op(op, addr) \ +({ \ + __asm__ __volatile__( \ + ".set push\n\t" \ + ".set noreorder\n\t" \ + ".set mips32\n\t" \ + "cache %0, %1\n\t" \ + ".set mips0\n\t" \ + ".set pop\n\t" \ + : \ + : "i" (op), "R" (*(unsigned char *)(addr))); \ +}) + +void perform_cache_operation(uintptr_t start, size_t size, uint8_t operation) +{ + u32 line_size, line_mask; + uintptr_t end; + + line_size = get_icache_line(); + line_mask = ~(line_size-1); + end = (start + (line_size - 1) + size) & line_mask; + start &= line_mask; + if ((operation & L2CACHE) == L2CACHE) + clear_L2tag(); + while (start < end) { + switch (operation) { + case CACHE_CODE(ICACHE, WB_INVD): + cache_op(CACHE_CODE(ICACHE, WB_INVD), start); + break; + case CACHE_CODE(DCACHE, WB_INVD): + cache_op(CACHE_CODE(DCACHE, WB_INVD), start); + break; + case CACHE_CODE(L2CACHE, WB_INVD): + cache_op(CACHE_CODE(L2CACHE, WB_INVD), start); + break; + default: + return; + } + start += line_size; + } + asm("sync"); +} + +void cache_invalidate_all(uintptr_t start, size_t size) +{ + perform_cache_operation(start, size, CACHE_CODE(ICACHE, WB_INVD)); + perform_cache_operation(start, size, CACHE_CODE(DCACHE, WB_INVD)); + perform_cache_operation(start, size, CACHE_CODE(L2CACHE, WB_INVD)); + +} diff --git a/src/arch/mips/include/arch/cache.h b/src/arch/mips/include/arch/cache.h index a9857414ce..8c7b6f1aeb 100644 --- a/src/arch/mips/include/arch/cache.h +++ b/src/arch/mips/include/arch/cache.h @@ -20,4 +20,33 @@ #ifndef __MIPS_ARCH_CACHE_H #define __MIPS_ARCH_CACHE_H +#include <stddef.h> +#include <stdint.h> + +#define get_icache_line() __get_line_size($16, 1, 19, 3) +#define get_dcache_line() __get_line_size($16, 1, 10, 3) +#define get_L2cache_line() __get_line_size($16, 2, 20, 4) + +#define CACHE_TYPE_SHIFT (0) +#define CACHE_OP_SHIFT (2) +#define CACHE_TYPE_MASK (0x3) +#define CACHE_OP_MASK (0x7) + +/* Cache type */ +#define ICACHE 0x00 +#define DCACHE 0x01 +#define L2CACHE 0x03 + +/* Cache operation*/ +#define WB_INVD 0x05 + +#define CACHE_CODE(type, op) ((((type) & (CACHE_TYPE_MASK)) << \ + (CACHE_TYPE_SHIFT)) | \ + (((op) & (CACHE_OP_MASK)) << (CACHE_OP_SHIFT))) + +/* Perform cache operation on cache lines for target addresses */ +void perform_cache_operation(uintptr_t start, size_t size, uint8_t operation); +/* Invalidate all caches: instruction, data, L2 data */ +void cache_invalidate_all(uintptr_t start, size_t size); + #endif /* __MIPS_ARCH_CACHE_H */ diff --git a/src/arch/mips/stages.c b/src/arch/mips/stages.c index 79b2ea4cd8..d6b36afe67 100644 --- a/src/arch/mips/stages.c +++ b/src/arch/mips/stages.c @@ -28,8 +28,5 @@ void stage_entry(void) void stage_exit(void *addr) { void (*doit)(void) = addr; - - /* TODO: synci */ - doit(); } |