diff options
| -rw-r--r-- | src/northbridge/amd/agesa/agesawrapper.h | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/agesa/family12/agesawrapper.c | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/agesa/family15/agesawrapper.c | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/pi/agesawrapper.h | 2 |
4 files changed, 2 insertions, 6 deletions
diff --git a/src/northbridge/amd/agesa/agesawrapper.h b/src/northbridge/amd/agesa/agesawrapper.h index 421212e743..6649eb9a85 100644 --- a/src/northbridge/amd/agesa/agesawrapper.h +++ b/src/northbridge/amd/agesa/agesawrapper.h @@ -24,8 +24,6 @@ #include "Porting.h" #include "AGESA.h" -#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS - enum { PICK_DMI, /* DMI Interface */ PICK_PSTATE, /* Acpi Pstate SSDT Table */ diff --git a/src/northbridge/amd/agesa/family12/agesawrapper.c b/src/northbridge/amd/agesa/family12/agesawrapper.c index 0c441eee35..f25e7379a9 100644 --- a/src/northbridge/amd/agesa/family12/agesawrapper.c +++ b/src/northbridge/amd/agesa/family12/agesawrapper.c @@ -151,7 +151,7 @@ AGESA_STATUS agesawrapper_amdinitcpuio(VOID) PciData = 0x00FFFF00 | 0x80; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xB8); - PciData = (PCIE_BASE_ADDRESS >> 8) | 03; + PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) | 03; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */ PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); diff --git a/src/northbridge/amd/agesa/family15/agesawrapper.c b/src/northbridge/amd/agesa/family15/agesawrapper.c index 0552a02303..2bc3e959d8 100644 --- a/src/northbridge/amd/agesa/family15/agesawrapper.c +++ b/src/northbridge/amd/agesa/family15/agesawrapper.c @@ -136,7 +136,7 @@ AGESA_STATUS agesawrapper_amdinitcpuio(void) PciData |= sblink << 4; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xB8); - PciData = (PCIE_BASE_ADDRESS >> 8) | 0x03; + PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) | 0x03; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Set PCIO: 0x0 - 0xFFF000 to Node0 sbLink and enabled VGA IO */ diff --git a/src/northbridge/amd/pi/agesawrapper.h b/src/northbridge/amd/pi/agesawrapper.h index d6558c45cc..eefde35746 100644 --- a/src/northbridge/amd/pi/agesawrapper.h +++ b/src/northbridge/amd/pi/agesawrapper.h @@ -24,8 +24,6 @@ #include "Porting.h" #include "AGESA.h" -#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS - enum { PICK_DMI, /* DMI Interface */ PICK_PSTATE, /* Acpi Pstate SSDT Table */ |