diff options
| -rw-r--r-- | src/cpu/intel/model_106cx/model_106cx_init.c | 17 | ||||
| -rw-r--r-- | src/mainboard/foxconn/d41s/cmos.layout | 1 | ||||
| -rw-r--r-- | src/mainboard/intel/d510mo/cmos.layout | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/pineview/Kconfig | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/pineview/northbridge.c | 22 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/lpc.c | 5 |
6 files changed, 2 insertions, 45 deletions
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 24a9ad29f6..75e110683e 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -17,12 +17,9 @@ #include <device/device.h> #include <string.h> #include <cpu/cpu.h> -#include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> -#include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> -#include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include <cpu/intel/common/common.h> @@ -84,20 +81,10 @@ static void model_106cx_init(struct device *cpu) /* Turn on caching if we haven't already */ x86_enable_cache(); - /* Update the microcode */ - if (!IS_ENABLED(CONFIG_PARALLEL_MP)) - intel_update_microcode_from_cbfs(); - /* Print processor name */ fill_processor_name(processor_name); printk(BIOS_INFO, "CPU: %s.\n", processor_name); - /* Setup MTRRs */ - if (!IS_ENABLED(CONFIG_PARALLEL_MP)) { - x86_setup_mtrrs(); - x86_mtrr_check(); - } - /* Enable the local CPU APICs */ setup_lapic(); @@ -111,10 +98,6 @@ static void model_106cx_init(struct device *cpu) configure_misc(); /* TODO: PIC thermal sensor control */ - - /* Start up my CPU siblings */ - if (!IS_ENABLED(CONFIG_PARALLEL_MP)) - intel_sibling_init(cpu); } static struct device_operations cpu_dev_ops = { diff --git a/src/mainboard/foxconn/d41s/cmos.layout b/src/mainboard/foxconn/d41s/cmos.layout index 9b9a084fc0..b006973cc3 100644 --- a/src/mainboard/foxconn/d41s/cmos.layout +++ b/src/mainboard/foxconn/d41s/cmos.layout @@ -44,7 +44,6 @@ entries 416 512 s 0 boot_devices # coreboot config options: cpu -944 1 e 2 hyper_threading #945 7 r 0 unused # coreboot config options: northbridge diff --git a/src/mainboard/intel/d510mo/cmos.layout b/src/mainboard/intel/d510mo/cmos.layout index 9b9a084fc0..b006973cc3 100644 --- a/src/mainboard/intel/d510mo/cmos.layout +++ b/src/mainboard/intel/d510mo/cmos.layout @@ -44,7 +44,6 @@ entries 416 512 s 0 boot_devices # coreboot config options: cpu -944 1 e 2 hyper_threading #945 7 r 0 unused # coreboot config options: northbridge diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index 6168305f7a..b5925012a3 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -31,6 +31,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select POSTCAR_STAGE select POSTCAR_CONSOLE select SMM_TSEG + select PARALLEL_MP config BOOTBLOCK_NORTHBRIDGE_INIT string diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index ee1efd3b1e..ec2c902b90 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -151,26 +151,6 @@ void northbridge_write_smram(u8 smram) pci_write_config8(dev, SMRAM, smram); } -/* - * Really doesn't belong here but will go away with parallel mp init, - * so let it be here for a while... - */ -int cpu_get_apic_id_map(int *apic_id_map) -{ - unsigned int i; - - /* Logical processors (threads) per core */ - const struct cpuid_result cpuid1 = cpuid(1); - /* Read number of cores. */ - const char cores = (cpuid1.ebx >> 16) & 0xf; - - /* TODO in parallel MP cpuid(1).ebx */ - for (i = 0; i < cores; i++) - apic_id_map[i] = i; - - return cores; -} - static void mch_domain_set_resources(struct device *dev) { struct resource *res; @@ -218,7 +198,7 @@ static struct device_operations pci_domain_ops = { static void cpu_bus_init(struct device *dev) { - initialize_cpus(dev->link_list); + bsp_init_and_start_aps(dev->link_list); } static struct device_operations cpu_bus_ops = { diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 5ad05c73ad..7497c7968c 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -350,11 +350,6 @@ static void i82801gx_lock_smm(struct device *dev) printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); outb(APM_CNT_ACPI_ENABLE, APM_CNT); } - /* Don't allow evil boot loaders, kernels, or - * userspace applications to deceive us: - */ - if (!IS_ENABLED(CONFIG_PARALLEL_MP)) - smm_lock(); #if TEST_SMM_FLASH_LOCKDOWN /* Now try this: */ |