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-rw-r--r--src/northbridge/intel/i945/early_init.c7
-rw-r--r--src/northbridge/intel/i945/raminit.c39
2 files changed, 1 insertions, 45 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index f388330f94..a8c160a22d 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -364,7 +364,7 @@ static void i945_setup_dmi_rcrb(void)
printk(BIOS_DEBUG, "timeout!\n");
else
printk(BIOS_DEBUG, "done..\n");
-#if 1
+
/* Enable Active State Power Management (ASPM) L0 state */
reg32 = DMIBAR32(DMILCAP);
@@ -387,7 +387,6 @@ static void i945_setup_dmi_rcrb(void)
if (activate_aspm)
DMIBAR32(DMILCTL) |= (3 << 0);
-#endif
/* Last but not least, some additional steps */
reg32 = MCHBAR32(FSBSNPCTL);
@@ -771,10 +770,6 @@ static void ich7_setup_pci_express(void)
/* Initialize slot power limit for root ports */
pci_write_config32(PCI_DEV(0, 0x1c, 0), 0x54, 0x00000060);
-#if 0
- pci_write_config32(PCI_DEV(0, 0x1c, 4), 0x54, 0x00480ce0);
- pci_write_config32(PCI_DEV(0, 0x1c, 5), 0x54, 0x00500ce0);
-#endif
pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000);
}
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 1c7a1f0769..cfe4d8f1c8 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -194,19 +194,6 @@ static int sdram_capabilities_enhanced_addressing_xor(void)
return (!reg8);
}
-/* TODO check if we ever need this function */
-#if 0
-static int sdram_capabilities_MEM4G_disable(void)
-{
- u8 reg8;
-
- reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
- reg8 &= (1 << 0);
-
- return (reg8 != 0);
-}
-#endif
-
#define GFX_FREQUENCY_CAP_166MHZ 0x04
#define GFX_FREQUENCY_CAP_200MHZ 0x03
#define GFX_FREQUENCY_CAP_250MHZ 0x02
@@ -2198,11 +2185,7 @@ static void sdram_power_management(struct sys_info *sysinfo)
reg16 |= (4 << 11);
MCHBAR16(CPCTL) = reg16;
-#if 0
- if ((MCHBAR32(ECO) & (1 << 16)) != 0) {
-#else
if (i945_silicon_revision() != 0) {
-#endif
switch (sysinfo->fsb_frequency) {
case 667:
MCHBAR32(HGIPMC2) = 0x0d590d59;
@@ -2253,13 +2236,6 @@ static void sdram_power_management(struct sys_info *sysinfo)
else
MCHBAR32(ECO) |= (1 << 16);
-#if 0
-
- if (i945_silicon_revision() == 0)
- MCHBAR32(FSBPMC3) &= ~(1 << 29);
- else
- MCHBAR32(FSBPMC3) |= (1 << 29);
-#endif
MCHBAR32(FSBPMC3) &= ~(1 << 29);
MCHBAR32(FSBPMC3) |= (1 << 21);
@@ -2288,19 +2264,6 @@ static void sdram_power_management(struct sys_info *sysinfo)
pci_or_config8(PCI_DEV(0, 0x2, 0), 0xc1, 1 << 2);
-#ifdef C2_SELF_REFRESH_DISABLE
-
- if (integrated_graphics) {
- printk(BIOS_DEBUG, "C2 self-refresh with IGD\n");
- MCHBAR16(MIPMC4) = 0x0468;
- MCHBAR16(MIPMC5) = 0x046c;
- MCHBAR16(MIPMC6) = 0x046c;
- } else {
- MCHBAR16(MIPMC4) = 0x6468;
- MCHBAR16(MIPMC5) = 0x646c;
- MCHBAR16(MIPMC6) = 0x646c;
- }
-#else
if (integrated_graphics) {
MCHBAR16(MIPMC4) = 0x04f8;
MCHBAR16(MIPMC5) = 0x04fc;
@@ -2311,8 +2274,6 @@ static void sdram_power_management(struct sys_info *sysinfo)
MCHBAR16(MIPMC6) = 0x64fc;
}
-#endif
-
reg32 = MCHBAR32(PMCFG);
reg32 &= ~(3 << 17);
reg32 |= (2 << 17);