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-rw-r--r--src/console/Kconfig21
-rw-r--r--src/mainboard/gigabyte/ga_2761gxdk/romstage.c4
-rw-r--r--src/mainboard/gigabyte/m57sli/romstage.c4
-rw-r--r--src/mainboard/msi/ms7260/romstage.c4
-rw-r--r--src/mainboard/msi/ms9652_fam10/romstage.c4
-rw-r--r--src/mainboard/nvidia/l1_2pvv/romstage.c4
-rw-r--r--src/mainboard/tyan/s2912/romstage.c4
-rw-r--r--src/mainboard/tyan/s2912_fam10/romstage.c4
8 files changed, 28 insertions, 21 deletions
diff --git a/src/console/Kconfig b/src/console/Kconfig
index fa6f840035..3b8fb02dca 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -112,6 +112,27 @@ config USBDEBUG
If unsure, say N.
+# Note: This option doesn't make sense on Intel ICH southbridges as those
+# hardcode the physical USB port to be used as Debug Port to 1. It cannot
+# be changed by coreboot.
+config USBDEBUG_DEFAULT_PORT
+ int "Default USB port to use as Debug Port"
+ default 1
+ depends on USBDEBUG && !SOUTHBRIDGE_INTEL_I82801GX
+ help
+ This option selects which physical USB port coreboot will try to
+ use as EHCI Debug Port first (valid values are: 1-15).
+
+ If coreboot doesn't detect an EHCI Debug Port dongle on this port,
+ it will try all the other ports one after the other. This will take
+ a few seconds of time though, and thus slow down the booting process.
+
+ Hence, if you select the correct port here, you can speed up
+ your boot time. Which USB port number (1-15) refers to which
+ actual port on your mainboard (potentially also USB pin headers
+ on your mainboard) is highly board-specific, and you'll likely
+ have to find out by trial-and-error.
+
config CONSOLE_VGA
bool "Use VGA console once initialized"
default n
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index e4762bfd09..cf5c6bda26 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -40,8 +40,6 @@
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
-#define DBGP_DEFAULT 7
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -196,7 +194,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
report_bist_failure(bist);
#if CONFIG_USBDEBUG
- sis966_enable_usbdebug(DBGP_DEFAULT);
+ sis966_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
early_usbdebug_init();
#endif
console_init();
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index e37d81e8a0..be5e46ba1a 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -38,8 +38,6 @@
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
-#define DBGP_DEFAULT 7
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -212,7 +210,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
report_bist_failure(bist);
#if CONFIG_USBDEBUG
- mcp55_enable_usbdebug(DBGP_DEFAULT);
+ mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
early_usbdebug_init();
#endif
console_init();
diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index 1f0738fb69..908138a5d3 100644
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -42,8 +42,6 @@
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
-#define DBGP_DEFAULT 7
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -181,7 +179,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
uart_init();
report_bist_failure(bist); /* Halt upon BIST failure. */
#if CONFIG_USBDEBUG
- mcp55_enable_usbdebug(DBGP_DEFAULT);
+ mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
early_usbdebug_init();
#endif
console_init();
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index 4b7fe8f1c7..2c448bd204 100644
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -33,8 +33,6 @@
#define SET_FIDVID 1
#define SET_FIDVID_CORE_RANGE 0
-#define DBGP_DEFAULT 7
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -185,7 +183,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
report_bist_failure(bist);
#if CONFIG_USBDEBUG
- mcp55_enable_usbdebug(DBGP_DEFAULT);
+ mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
early_usbdebug_init();
#endif
diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index dfdc57c742..bdc6810086 100644
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -38,8 +38,6 @@
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
-#define DBGP_DEFAULT 7
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -198,7 +196,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
report_bist_failure(bist);
#if CONFIG_USBDEBUG
- mcp55_enable_usbdebug(DBGP_DEFAULT);
+ mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
early_usbdebug_init();
#endif
console_init();
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index 6548f77e62..695d2cbe8a 100644
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -38,8 +38,6 @@
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
-#define DBGP_DEFAULT 7
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -192,7 +190,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
report_bist_failure(bist);
#if CONFIG_USBDEBUG
- mcp55_enable_usbdebug(DBGP_DEFAULT);
+ mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
early_usbdebug_init();
#endif
console_init();
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index 5792d34af7..ed79299e8c 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -33,8 +33,6 @@
#define SET_FIDVID 1
#define SET_FIDVID_CORE_RANGE 0
-#define DBGP_DEFAULT 7
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -180,7 +178,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
report_bist_failure(bist);
#if CONFIG_USBDEBUG
- mcp55_enable_usbdebug(DBGP_DEFAULT);
+ mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
early_usbdebug_init();
#endif
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-19 18:19:13 +0000